在HyperBGA/sup /spl reg//封装上12.5 Gb/s的建模与仿真

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI:10.1109/IEMT.2003.1225891

R.D. McBride, S. Rosser, R. P. Nowak

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引用次数: 13

摘要

本文介绍了Endicott Interconnect Technologies的HyperBGA/sup /spl reg//有机芯片载波封装的高速/高频建模和仿真结果。利用业界领先的先进软件工具，Ansoft Links/sup TM/、Ansoft HFSS/sup TM/和Ansoft Serenade/sup /spl reg//，这项建模和仿真工作已经证明，目前的HyperBGA/sup /spl reg//技术将满足以每通道12.5 Gb/s的速度运行的应用程序的性能要求。在整个讨论过程中，揭示了一般的建模和模拟方法，以及建模的实际物理结构和所涉及的固有假设和边界条件。

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Modeling and simulation of 12.5 Gb/s on a HyperBGA/sup /spl reg// package

This paper presents high-speed/high-frequency modeling and simulation results for Endicott Interconnect Technologies' HyperBGA/sup /spl reg// organic chip-carrier package. Utilizing industry leading advanced software tools, Ansoft Links/sup TM/, Ansoft HFSS/sup TM/, and Ansoft Serenade/sup /spl reg//, this modeling and simulation effort has demonstrated that current HyperBGA/sup /spl reg// technology will meet the performance requirements for applications running at speeds of 12.5 Gb/s per channel. Throughout the course of this discussion, the general modeling and simulation methodology is revealed, along with the actual physical structures modeled and the inherent assumptions and boundary conditions involved.

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来源期刊

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.

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