IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.最新文献_第7页

Processing and reliability of corner bonded CSPs 角键合csp的加工与可靠性

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225917

B. Toleno, J. Schneider

{"title":"Processing and reliability of corner bonded CSPs","authors":"B. Toleno, J. Schneider","doi":"10.1109/IEMT.2003.1225917","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225917","url":null,"abstract":"Chip scale packages (CSPs) are now widely used for many electronic applications including portable electronics, telecommunications, and automotive assemblies. Assemblers of these types of devices are looking for solutions that both decrease cost and increase reliability. Underfilling CSPs is known to increase the reliability of these devices. This process can be costly in materials, capital equipment, and process time. This paper presents an alternate solution, bonding the CSP at the corners and edges. This process is used to increase the reliability of CSP devices with respect to shock and vibration. The corner bonding material examined in this study can be dispensed prior to reflow along side the solder paste onto the substrate and cured during the reflow process. This paper will discuss the processing aspects and the reliability of the bonded device. Processing parameters to be discussed are the maximum displacement that allows self-alignment, the optimum placement of the corner bond material on packages with corner bumps will be presented, and dot diameter and heights. The second half of the paper discusses the reliability performance of the material in comparison with several traditional underfill materials. Reliability testing included performing drop testing and thermal cycling (-55/spl deg/C to +125/spl deg/C) on test vehicles. These studies were conducted are several sizes of components from a 35 mm/spl times/35 mm, 1.27 mm pitch, PBGA down to a 6 mm/spl times/8 mm, 0.75 mm microBGA.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115194388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Time dependant materials issues in the electromigration of solder bumps 焊料凸点电迁移中与时间相关的材料问题

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225895

G. Rinne

引用次数: 0

Equipment failure definition: a prerequisite for reliability test and validation 设备故障定义:可靠性测试和验证的先决条件

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225929

A. Fashandi, T. Umberg

引用次数: 8

Laser dicing of chip scale and silicon wafer scale packages 芯片级和硅片级封装的激光切割

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225869

T. Lizotte

{"title":"Laser dicing of chip scale and silicon wafer scale packages","authors":"T. Lizotte","doi":"10.1109/IEMT.2003.1225869","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225869","url":null,"abstract":"Singulation of PCB based chip scale packages as well as the dicing of silicon based flip chip or wafer scale packaging is becoming critical. With the use of batch processes for PCB circuit fabrication and chip mounting, it becomes highly desirable to move away from standard diamond blade dicing techniques. The advent of silicon based packaging and wafers with a variety of odd form factor silicon chips and custom ASIC devices have caused further limitations to be encountered during dicing. It was inevitable that the inherent limitations of fixed row and column diamond saws would lead to the development and acceptance of free form trepanning capabilities offered by laser dicing and/or singulation. This paper will cover laser dicing and/or singulation of both chip scale and wafer scale-packaging materials. Initially the paper will outline material types with an emphasis on laser materials interactions and the selection of appropriate laser wavelengths for optimum process performance. Further explanations, formulas and basic laser nomenclature will also be discussed to familiarize those individuals who do not have experience with laser technology. The main body of the paper will focus on process parameters, processing rates, debris mitigation techniques, beam delivery configurations, substrate mounting, lasers types and cut quality achieved in the various materials outlined in the first section of the paper. The final section of the paper will summarize the quality of the process and the associated costs of using laser technology as compared to diamond saw technology.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134353861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

System availability and operation support modeling 系统可用性和操作支持建模

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225927

A. Fashandi

引用次数: 1

A design and performance study of 3D packaging for high performance memory applications 用于高性能存储器应用的3D封装设计与性能研究

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225892

I. Mohammed, Byongsu Seol, S. Krishnan

{"title":"A design and performance study of 3D packaging for high performance memory applications","authors":"I. Mohammed, Byongsu Seol, S. Krishnan","doi":"10.1109/IEMT.2003.1225892","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225892","url":null,"abstract":"To address the performance and miniaturization challenges being faced by the packaging industry, a novel packaging methodology is presented in this paper. A 3D packaging methodology that leverages the existing CSP (Chip Scale Packaging) infrastructure to design and build memory solutions that is high performing and highly dense is presented. The design includes the individual device package design, the 3D package design and module design. Both the electrical and thermal performance is optimized by modifying the three levels of design. The design trade-offs are studied in terms of performance and compared to the performance of single device packages. The 3D packages are analyzed electrically and thermally using finite element and finite difference-based commercial software. The electrical performance results are presented at a single device level and at the 3D package level. The thermal performance is determined under standard test conditions and actual operating environments. Finally, to illustrate the 3D packaging technique, a compact memory module is presented that offers high performance, has a low profile and enables dense memory systems.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"603 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116349803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Process challenges in low-k wafer dicing 低钾晶圆切割的工艺挑战

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225935

Hanxie Zhao, D. Shi

{"title":"Process challenges in low-k wafer dicing","authors":"Hanxie Zhao, D. Shi","doi":"10.1109/IEMT.2003.1225935","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225935","url":null,"abstract":"Rapid developments in semiconductor industry and the need to maintain interconnect performance as feature sizes shrink are driving a transition to low dielectric constant (k) materials. The very different chemistries and materials properties of low-k dielectric materials may impose novel challenges to wafer/chip manufacturing and packaging processes. Process integration thus becomes more difficult due to the profound changes in properties compared with traditional dielectric materials. Dicing (or sawing) is the first step in the packaging process and its quality can have a significant impact on yields, as well as on device reliability. This paper describes dicing of eight types of Spin-On and CVD low-k wafers. Effects of various blades and dicing process parameters, as well as their combined effect on quality and yield, are discussed. In addition, the effect of cut depth is also examined. Various problems encountered in low-k wafer dicing are presented, and considerations and potential solutions for overcoming these quality obstacles in low-k wafer dicing are discussed. The study shows that the optimized dicing processes must be based on the actual low-k materials, wafer structures and process history of the low-k wafers.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117067702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

The role of laminate, LTCC, and silicon based approaches to system in package development 层压板、LTCC和硅基方法在封装开发中的作用

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225909

E. Law, D. Kossives, K. Bailey, D. Sahakian, J. Ling, R. Emigh

引用次数: 3

New test approaches for zero-IF transceiver devices 零中频收发器器件的新测试方法

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225937

J. Lukez

引用次数: 8

Considerations for minimizing radiation doses to components during X-ray inspection 在x射线检查中尽量减少对组件的辐射剂量的考虑

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 1900-01-01 DOI: 10.1109/IEMT.2003.1225931

D. Bernard, R. Blish

{"title":"Considerations for minimizing radiation doses to components during X-ray inspection","authors":"D. Bernard, R. Blish","doi":"10.1109/IEMT.2003.1225931","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225931","url":null,"abstract":"The ability to undertake non-destructive testing on semiconductor devices, during both their manufacture and their subsequent use in printed circuit boards (PCBs), has become ever more important for checking product quality without compromising productivity. The use of X-ray inspection not only provides a potentially non-destructive test but also allows investigation within optically hidden areas, such as the wire bonding within packages and the quality of post solder reflow of area array devices (e.g. BGAs, CSPs and flip chips). During X-ray inspection the sample is bathed in the ionizing radiation of high-energy photons, so the sample receives a radiation dose. Certain devices are susceptible to damage by ionizing radiation. Therefore, this susceptibility may require the user to consider the radiation dose being given to these items during the X-ray inspection process to ensure critical thresholds are not exceeded. This paper will discuss the issues that a user of these radiation-sensitive components may wish to consider, together with practical suggestions as to how to measure and minimize the radiation dose for best practice during X-ray examination.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115721885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6