A new wafer level package for improved electrical and reliability performance

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI:10.1109/IEMT.2003.1225893

S. Barrett, J. Reche, Deok-Hoon Kim, D. Stepniak

{"title":"A new wafer level package for improved electrical and reliability performance","authors":"S. Barrett, J. Reche, Deok-Hoon Kim, D. Stepniak","doi":"10.1109/IEMT.2003.1225893","DOIUrl":null,"url":null,"abstract":"Wafer level packages (WLPs) have demonstrated a very clear size and cost advantage vs. traditional wirebond technologies, especially for small components that have a high number of dice and I/O per wafer. The Kulicke & Soffa Flip Chip Division (FCD) introduced it's first WLP in 1998. This initial WLP utilized a bump on nitride structure (BON) which had good reliability but also high input capacitance. A new WLP has been developed by FCD. This new WLP has a solder bump on polymer (BOP) dielectric structure. A major driver for pursuing a BOP structure was to achieve minimal input capacitance for high speed applications. During development, a new polymer dielectric material was carefully selected based on reliability tests and manufacturability. Thermal Cycling (TC) test showed 30% better TC performance vs. the BON structure. The new WLP also passed 168 hours of autoclave and JEDEC Level 1 Preconditioning testing. In this paper, the advantages of this new WLP will be discussed in detail. In addition, reliability test results will be presented.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.2003.1225893","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

Abstract

Wafer level packages (WLPs) have demonstrated a very clear size and cost advantage vs. traditional wirebond technologies, especially for small components that have a high number of dice and I/O per wafer. The Kulicke & Soffa Flip Chip Division (FCD) introduced it's first WLP in 1998. This initial WLP utilized a bump on nitride structure (BON) which had good reliability but also high input capacitance. A new WLP has been developed by FCD. This new WLP has a solder bump on polymer (BOP) dielectric structure. A major driver for pursuing a BOP structure was to achieve minimal input capacitance for high speed applications. During development, a new polymer dielectric material was carefully selected based on reliability tests and manufacturability. Thermal Cycling (TC) test showed 30% better TC performance vs. the BON structure. The new WLP also passed 168 hours of autoclave and JEDEC Level 1 Preconditioning testing. In this paper, the advantages of this new WLP will be discussed in detail. In addition, reliability test results will be presented.

查看原文本刊更多论文

一个新的晶圆级封装，提高电气和可靠性性能

与传统的线键技术相比，晶圆级封装(wlp)已经显示出非常明显的尺寸和成本优势，特别是对于每个晶圆具有大量芯片和I/O的小型组件。Kulicke & sofa倒装芯片部门(FCD)于1998年推出了它的第一个WLP。最初的WLP采用了氮化结构(BON)，具有良好的可靠性和高输入电容。FCD开发了一种新的WLP。这种新型WLP在聚合物(BOP)介电结构上具有焊料凸起。追求防喷器结构的主要驱动力是实现高速应用所需的最小输入电容。在开发过程中，根据可靠性测试和可制造性，精心选择了一种新型聚合物介电材料。热循环(TC)测试表明，与BON结构相比，TC性能提高了30%。新的WLP还通过了168小时的高压灭菌器和JEDEC 1级预处理测试。本文将详细讨论这种新型WLP的优点。此外，还将给出可靠性测试结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.

自引率

0.00%

发文量