Validating and characterizing high speed datacom devices

Abstract

ICs developed for data communications present a number of challenges in the development of test solutions to be used in validation, characterization, and high volume production. One of the most obvious challenges is the frequency and data rates at which these devices operate. The OC-48 standard in use today transmits and receives data at 2.5 Gbps. Emerging standards of "Xaui" and "OC-192" operate at 3.2 Gbps and 9.6 Gbps respectively, which provide even greater challenges. The majority of ATE today operates at /spl Lt/1 Gbps. A few ATE companies have announced solutions that will be able to provide at 3.2 Gbps, but these solutions are hard to find. Other challenges are jitter requirements as low as 5pS, non-deterministic data delays in the devices, signal pin counts above 500 pins, and low voltage differential swings. This paper looks at these challenges and solutions. The results from OC-48, Xaui, and OC-192 projects developed by NPTest SABER will be presented. These solutions use a combination of ATE, external instrumentation, custom interfacing, and software. The paper will also look at tradeoffs in these solutions.