Next generation electronics packaging utilizing flip chip technology

Abstract

This paper discusses the critical requirements for high volume flip chip die bonding. Product functionality for devices such as handheld telephones, laptop computers, and other personal electronic items has driven a trend towards compactness of design and improved packaging processes. The paper presents an overview of products and technologies utilizing flip chip packaging techniques today and in the future. It includes a discussion of the technical and cost drivers of flip chip packaging. Flip chip technology offers design and processing advantages. Design advantages include smaller device footprint, improved electrical performance, better thermal dissipation properties and lower cost due to better use of silicon real estate. Processing advantages include shorter assembly cycle times, fewer operations, and higher yields. A range of packages is available for flip chip packaging including FC-CSP, FC-BGA, HFC-BGA, and others. A comparison of these packages is presented including a comparison of I/O count and package size. The paper describes the advantages and applications for each of these package types. The methodology of flip chip die bonding is rooted in die bonding with some interesting modifications. Key components of the flip chip process are substrate handling along with die flipping and flux dipping. These process steps are presented with a detailed description from the initial point of picking the die through fluxing and to the actual placement of the die including material handling. Critical aspects of the flip chip die bonding process such as work holder planarity and flux control are discussed as the key to high yield, high volume production. Critical aspects of underfill dispensing such as process control and high throughputs are presented as the key to cost effective production.