{"title":"MEMS technology: optical application, medical application and SOC application","authors":"M. Esashi","doi":"10.1109/VLSIT.2002.1015366","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015366","url":null,"abstract":"MEMS (micro electromechanical systems) have been developed based on silicon bulk micromachining. Wafer process packaging was applied to an electrostatically levitated rotational gyroscope and a micro relay. High density electrical feedthrough made by glass deep RIE and metal electroplating enabled an array MEMS as multiprobe data storage and contactor for LSI probing. Fine diameter fiber optic sensors for pressure and NSOM (near field scanning optical microscope) sensor applications were developed. The hydrogen storage capacity of a carbon nanotube was measured using the resonant frequency shift of a thin silicon cantilever.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126300552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Tomita, K. Hashimoto, T. Inbe, T. Oashi, K. Tsukamoto, Y. Nishioka, M. Matsuura, T. Eimori, M. Inuishi, I. Miyanaga, M. Nakamura, T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya, M. Ogura
{"title":"Sub-1 /spl mu/m/sup 2/ high density embedded SRAM technologies for 100 nm generation SOC and beyond","authors":"K. Tomita, K. Hashimoto, T. Inbe, T. Oashi, K. Tsukamoto, Y. Nishioka, M. Matsuura, T. Eimori, M. Inuishi, I. Miyanaga, M. Nakamura, T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya, M. Ogura","doi":"10.1109/VLSIT.2002.1015369","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015369","url":null,"abstract":"We have integrated a high speed and high density 6T-SRAM cell (0.998 /spl mu/m/sup 2/) for system-on-a-chip (SOC) using enhanced 100 nm CMOS logic technology. This is achieved by a systematic integration methodology, which includes high-NA ArF lithography, optimized optical proximity correction (OPC) CAD, narrow well isolation, poly-buffered shallow trench isolation (STI), offset spacer transistor, and 9-level Cu interconnect and low-k dielectric technologies with the lithographically scalable SRAM cell design.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Mehrotra, J. Wu, A. Jain, T. Laaksonen, K. Kim, W. Bather, R. Koshy, J. Chen, J. Jacobs, V. Ukraintsev, L. Olsen, J. Deloach, J. Mehigan, R. Agarwal, S. Walsh, D. Sekel, L. Tsung, M. Vaidyanathan, B. Trentman, K. Liu, S. Aur, R. Khamankar, P. Nicollian, Q. Jiang, Y. Xu, B. Campbell, P. Tiner, R. Wise, D. Scott, M. Rodder
{"title":"60 nm gate length dual-Vt CMOS for high performance applications","authors":"M. Mehrotra, J. Wu, A. Jain, T. Laaksonen, K. Kim, W. Bather, R. Koshy, J. Chen, J. Jacobs, V. Ukraintsev, L. Olsen, J. Deloach, J. Mehigan, R. Agarwal, S. Walsh, D. Sekel, L. Tsung, M. Vaidyanathan, B. Trentman, K. Liu, S. Aur, R. Khamankar, P. Nicollian, Q. Jiang, Y. Xu, B. Campbell, P. Tiner, R. Wise, D. Scott, M. Rodder","doi":"10.1109/VLSIT.2002.1015419","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015419","url":null,"abstract":"In this work, we present a 60 nm gate length CMOS for high performance applications at the 0.13 /spl mu/m CMOS node. The technology utilizes 193 nm gate lithography, dual spacers with thin spacer before drain extension implant and L-shaped nitride spacer after drain extensions, and remote-plasma nitrided dielectric with 1.75 nm EOT. 10-15% improvement in drive current is achieved with lower series resistance by reduction of dopant loss and higher dopant activation, resulting in n- and pMOS I/sub drive/ of 1160 /spl mu/A//spl mu/m and 550 /spl mu/A//spl mu/m at 1.3 V at I/sub off/=100 nA//spl mu/m.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120934341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Morifuji, T. Kumamori, M. Muta, K. Suzuki, M. S. Krishnan, T. Brożek, X. Li, W. Asano, M. Nishigori, N. Yanagiya, S. Yamada, K. Miyamoto, T. Noguchi, M. Kakumu
{"title":"New guideline for hydrogen treatment in advanced system LSI","authors":"E. Morifuji, T. Kumamori, M. Muta, K. Suzuki, M. S. Krishnan, T. Brożek, X. Li, W. Asano, M. Nishigori, N. Yanagiya, S. Yamada, K. Miyamoto, T. Noguchi, M. Kakumu","doi":"10.1109/VLSIT.2002.1015459","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015459","url":null,"abstract":"In this paper, we focus on hydrogen related processes and its impact on system LSI. Hydrogen affects not only DRAM performance but also reliability characteristics for MOSFET such as NBTI (negative bias temperature instability), HCI (hot carrier injection), and TDDB. We demonstrate that NBTI and HCI are degraded by excess hydrogen while improving retention characteristics of eDRAM. It is shown for the first time that anomalous degradation in TDDB for downsized MOSFET is caused by the compressive stress by STI and shows strong correlation to hydrogen processes. The optimization of hydrogen processes is indispensable for highly reliable system LSI in future generations.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131401479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The effects of substrate coupling on triggering uniformity and ESD failure threshold of fully silicided NMOS transistors","authors":"Y. Huh, V. Axerad, J.W. Chen, P. Bendix","doi":"10.1109/VLSIT.2002.1015461","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015461","url":null,"abstract":"We present a multi-finger turn-on model incorporating substrate coupling effects in multi-finger NMOS transistors during ESD events. It is demonstrated that the substrate coupling enables uniform triggering in a multi-finger structure. In addition, we show that fully silicided transistors can be used successfully as an ESD protection device without any design/process options if the effective epi thickness is larger than 1.5 /spl mu/m or bulk wafer is used.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132980340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hot-carrier charge trapping and reliability in high-k dielectrics","authors":"A. Kumar, T. Ning, M. Fischetti, E. Gusev","doi":"10.1109/VLSIT.2002.1015430","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015430","url":null,"abstract":"This paper reports for the first time on hot-electron and hot-hole charge trapping in HfO/sub 2/ pFETs/nFETs and Al/sub 2/O/sub 3/ nFETs. We find that, for equivalent injected charge, trapping due to substrate hot holes in pFETs is far more severe than from holes injected by cold tunneling. Enhanced trapping due to hot electrons in the nFETs is also observed, but only in the presence of illumination. These observations are consistent with a picture in which hot holes act as a precursor for trap creation.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117179563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Samavedam, H. Tseng, P. Tobin, J. Mogab, S. Dakshina-Murthy, L. La, J. Smith, J. Schaeffer, M. Zavala, R. Martin, B. Nguyen, L. Hebert, O. Adetutu, V. Dhandapani, T. Luo, R. García, P. Abramowitz, M. Moosa, D. Gilmer, C. Hobbs, W. Taylor, J. Grant, R. Hegde, S. Bagchi, E. Luckowski, V. Arunachalam, M. Azrak
{"title":"Metal gate MOSFETs with HfO/sub 2/ gate dielectric","authors":"S. Samavedam, H. Tseng, P. Tobin, J. Mogab, S. Dakshina-Murthy, L. La, J. Smith, J. Schaeffer, M. Zavala, R. Martin, B. Nguyen, L. Hebert, O. Adetutu, V. Dhandapani, T. Luo, R. García, P. Abramowitz, M. Moosa, D. Gilmer, C. Hobbs, W. Taylor, J. Grant, R. Hegde, S. Bagchi, E. Luckowski, V. Arunachalam, M. Azrak","doi":"10.1109/VLSIT.2002.1015373","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015373","url":null,"abstract":"We report for the first time electrical characterization of HfO/sub 2/ p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration. Their performance is compared to PVD TiN-gated HfO/sub 2/ and SiO/sub 2/ n- and p-MOSFETs. To understand the issues with metal gates on high K gate dielectrics, PVD TiN MOSFETs were extensively characterized. At 10 nA//spl mu/m leakage, 0.345 mA//spl mu/m drive current was obtained from PVD TiN/HfO/sub 2/ p-MOSFETs. HfO/sub 2/ n-MOSFETs with metal gates show about 10/sup 4/ times reduction in gate leakage compared to poly/SiO/sub 2/ devices.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122166526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Q. Lu, H. Takeuchi, Xiaofan Meng, T. King, C. Hu, K. Onishi, Hag-ju Cho, J. Lee
{"title":"Improved performance of ultra-thin HfO/sub 2/ CMOSFETs using poly-SiGe gate","authors":"Q. Lu, H. Takeuchi, Xiaofan Meng, T. King, C. Hu, K. Onishi, Hag-ju Cho, J. Lee","doi":"10.1109/VLSIT.2002.1015400","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015400","url":null,"abstract":"Poly-SiGe is investigated as the gate material for CMOS transistors with ultra-thin HfO/sub 2/ gate dielectric. Compared with poly-Si, poly-SiGe reduces the gate depletion effect, and also results in thinner EOT of the gate dielectric after 1000/spl deg/C annealing, with low gate leakage maintained. The Si interface quality is also better than that achieved with surface nitridation, which has been used to reduce EOT. Therefore, the use of poly-SiGe as the gate material is effective for improving the performance of ultra-thin HfO/sub 2/ CMOS transistors.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130348485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Choi, B. Nam, J. Ku, D. Kim, S. Lee, J.J. Lee, J. Lee, J. Ryu, S. Heo, J.K. Cho, S. Yoon, C.J. Choi, Y.J. Lee, J. Chung, B.H. Kim, M.B. Lee, G. Choi, Y.S. Kim, K. Fujihara, U. Chung, J. Moon
{"title":"Highly manufacturable sub-100 nm DRAM integrated with full functionality","authors":"S. Choi, B. Nam, J. Ku, D. Kim, S. Lee, J.J. Lee, J. Lee, J. Ryu, S. Heo, J.K. Cho, S. Yoon, C.J. Choi, Y.J. Lee, J. Chung, B.H. Kim, M.B. Lee, G. Choi, Y.S. Kim, K. Fujihara, U. Chung, J. Moon","doi":"10.1109/VLSIT.2002.1015385","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015385","url":null,"abstract":"Sub-100 nm DRAM is successfully fabricated for the first time with several key technologies, including W/W/sub x/N-poly gate, bitline structure having low parasitic capacitance, Ru/Ta/sub 2/O/sub 5//poly-Si capacitor and advanced CVD-Al contact processes. A fully functional working device is obtained with promising cell performance. Each technology also shows its extendibility as a manufacturable module process for further scaled DRAM.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"10 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132974117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Yeap, J. Chen, P. Grudowski, Y. Jeon, Y. Shiho, W. Qi, S. Jallepalli, N. Ramani, K. Hellig, L. Vishnubhotla, T. Luo, H. Tseng, Y. Du, S. Lim, P. Abramowitz, C. Reddy, S. Parihar, R. Singh, M. Wright, K. Patterson, N. Benavides, D. Bonser, T. V. Gompel, J. Conner, J.J. Lee, M. Rendon, D. Hall, A. Nghiem, R. Stout, K. Weidemann, A. Duvallet, J. Alvis, D. Dyer, D. Burnett, P. Ingersoll, K. Wimmer, S. Veeraraghavan, M. Foisy, M. Hall, J. Pellerin, D. Wristers, M. Woo, C. Lage
{"title":"A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications","authors":"G. Yeap, J. Chen, P. Grudowski, Y. Jeon, Y. Shiho, W. Qi, S. Jallepalli, N. Ramani, K. Hellig, L. Vishnubhotla, T. Luo, H. Tseng, Y. Du, S. Lim, P. Abramowitz, C. Reddy, S. Parihar, R. Singh, M. Wright, K. Patterson, N. Benavides, D. Bonser, T. V. Gompel, J. Conner, J.J. Lee, M. Rendon, D. Hall, A. Nghiem, R. Stout, K. Weidemann, A. Duvallet, J. Alvis, D. Dyer, D. Burnett, P. Ingersoll, K. Wimmer, S. Veeraraghavan, M. Foisy, M. Hall, J. Pellerin, D. Wristers, M. Woo, C. Lage","doi":"10.1109/VLSIT.2002.1015370","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015370","url":null,"abstract":"We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design (M. Fukuma et al., VLSI Tech., 2000) techniques (e.g. well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/analog system on chip (SoC) applications. The transistor performances are comparable to or better than recently reported data at the 100 nm technology node. This technology also features an all-layer copper/low-k (<3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction (S. Parihar et al., Proc. IEDM, 2001).","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132055849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}