A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

Abstract

We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design (M. Fukuma et al., VLSI Tech., 2000) techniques (e.g. well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/analog system on chip (SoC) applications. The transistor performances are comparable to or better than recently reported data at the 100 nm technology node. This technology also features an all-layer copper/low-k (<3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction (S. Parihar et al., Proc. IEDM, 2001).