S. Choi, B. Nam, J. Ku, D. Kim, S. Lee, J.J. Lee, J. Lee, J. Ryu, S. Heo, J.K. Cho, S. Yoon, C.J. Choi, Y.J. Lee, J. Chung, B.H. Kim, M.B. Lee, G. Choi, Y.S. Kim, K. Fujihara, U. Chung, J. Moon
{"title":"高度可制造的亚100纳米DRAM集成了完整的功能","authors":"S. Choi, B. Nam, J. Ku, D. Kim, S. Lee, J.J. Lee, J. Lee, J. Ryu, S. Heo, J.K. Cho, S. Yoon, C.J. Choi, Y.J. Lee, J. Chung, B.H. Kim, M.B. Lee, G. Choi, Y.S. Kim, K. Fujihara, U. Chung, J. Moon","doi":"10.1109/VLSIT.2002.1015385","DOIUrl":null,"url":null,"abstract":"Sub-100 nm DRAM is successfully fabricated for the first time with several key technologies, including W/W/sub x/N-poly gate, bitline structure having low parasitic capacitance, Ru/Ta/sub 2/O/sub 5//poly-Si capacitor and advanced CVD-Al contact processes. A fully functional working device is obtained with promising cell performance. Each technology also shows its extendibility as a manufacturable module process for further scaled DRAM.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"10 9","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Highly manufacturable sub-100 nm DRAM integrated with full functionality\",\"authors\":\"S. Choi, B. Nam, J. Ku, D. Kim, S. Lee, J.J. Lee, J. Lee, J. Ryu, S. Heo, J.K. Cho, S. Yoon, C.J. Choi, Y.J. Lee, J. Chung, B.H. Kim, M.B. Lee, G. Choi, Y.S. Kim, K. Fujihara, U. Chung, J. Moon\",\"doi\":\"10.1109/VLSIT.2002.1015385\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Sub-100 nm DRAM is successfully fabricated for the first time with several key technologies, including W/W/sub x/N-poly gate, bitline structure having low parasitic capacitance, Ru/Ta/sub 2/O/sub 5//poly-Si capacitor and advanced CVD-Al contact processes. A fully functional working device is obtained with promising cell performance. Each technology also shows its extendibility as a manufacturable module process for further scaled DRAM.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"10 9\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015385\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015385","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Highly manufacturable sub-100 nm DRAM integrated with full functionality
Sub-100 nm DRAM is successfully fabricated for the first time with several key technologies, including W/W/sub x/N-poly gate, bitline structure having low parasitic capacitance, Ru/Ta/sub 2/O/sub 5//poly-Si capacitor and advanced CVD-Al contact processes. A fully functional working device is obtained with promising cell performance. Each technology also shows its extendibility as a manufacturable module process for further scaled DRAM.
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