60 nm gate length dual-Vt CMOS for high performance applications

Abstract

In this work, we present a 60 nm gate length CMOS for high performance applications at the 0.13 /spl mu/m CMOS node. The technology utilizes 193 nm gate lithography, dual spacers with thin spacer before drain extension implant and L-shaped nitride spacer after drain extensions, and remote-plasma nitrided dielectric with 1.75 nm EOT. 10-15% improvement in drive current is achieved with lower series resistance by reduction of dopant loss and higher dopant activation, resulting in n- and pMOS I/sub drive/ of 1160 /spl mu/A//spl mu/m and 550 /spl mu/A//spl mu/m at 1.3 V at I/sub off/=100 nA//spl mu/m.