衬底耦合对全硅化NMOS晶体管触发均匀性和ESD失效阈值的影响

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015461

Y. Huh, V. Axerad, J.W. Chen, P. Bendix

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引用次数: 8

摘要

我们提出了一个包含多指NMOS晶体管在ESD事件中衬底耦合效应的多指导通模型。结果表明，衬底耦合能够在多指结构中实现均匀触发。此外，我们表明，如果有效外延厚度大于1.5 /spl mu/m或使用块状晶圆，则完全硅化晶体管可以成功用作ESD保护器件，而无需任何设计/工艺选择。

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The effects of substrate coupling on triggering uniformity and ESD failure threshold of fully silicided NMOS transistors

We present a multi-finger turn-on model incorporating substrate coupling effects in multi-finger NMOS transistors during ESD events. It is demonstrated that the substrate coupling enables uniform triggering in a multi-finger structure. In addition, we show that fully silicided transistors can be used successfully as an ESD protection device without any design/process options if the effective epi thickness is larger than 1.5 /spl mu/m or bulk wafer is used.

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2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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