S. Samavedam, H. Tseng, P. Tobin, J. Mogab, S. Dakshina-Murthy, L. La, J. Smith, J. Schaeffer, M. Zavala, R. Martin, B. Nguyen, L. Hebert, O. Adetutu, V. Dhandapani, T. Luo, R. García, P. Abramowitz, M. Moosa, D. Gilmer, C. Hobbs, W. Taylor, J. Grant, R. Hegde, S. Bagchi, E. Luckowski, V. Arunachalam, M. Azrak
{"title":"Metal gate MOSFETs with HfO/sub 2/ gate dielectric","authors":"S. Samavedam, H. Tseng, P. Tobin, J. Mogab, S. Dakshina-Murthy, L. La, J. Smith, J. Schaeffer, M. Zavala, R. Martin, B. Nguyen, L. Hebert, O. Adetutu, V. Dhandapani, T. Luo, R. García, P. Abramowitz, M. Moosa, D. Gilmer, C. Hobbs, W. Taylor, J. Grant, R. Hegde, S. Bagchi, E. Luckowski, V. Arunachalam, M. Azrak","doi":"10.1109/VLSIT.2002.1015373","DOIUrl":null,"url":null,"abstract":"We report for the first time electrical characterization of HfO/sub 2/ p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration. Their performance is compared to PVD TiN-gated HfO/sub 2/ and SiO/sub 2/ n- and p-MOSFETs. To understand the issues with metal gates on high K gate dielectrics, PVD TiN MOSFETs were extensively characterized. At 10 nA//spl mu/m leakage, 0.345 mA//spl mu/m drive current was obtained from PVD TiN/HfO/sub 2/ p-MOSFETs. HfO/sub 2/ n-MOSFETs with metal gates show about 10/sup 4/ times reduction in gate leakage compared to poly/SiO/sub 2/ devices.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015373","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
We report for the first time electrical characterization of HfO/sub 2/ p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration. Their performance is compared to PVD TiN-gated HfO/sub 2/ and SiO/sub 2/ n- and p-MOSFETs. To understand the issues with metal gates on high K gate dielectrics, PVD TiN MOSFETs were extensively characterized. At 10 nA//spl mu/m leakage, 0.345 mA//spl mu/m drive current was obtained from PVD TiN/HfO/sub 2/ p-MOSFETs. HfO/sub 2/ n-MOSFETs with metal gates show about 10/sup 4/ times reduction in gate leakage compared to poly/SiO/sub 2/ devices.