Sub-1 /spl mu/m/sup 2/ high density embedded SRAM technologies for 100 nm generation SOC and beyond

K. Tomita, K. Hashimoto, T. Inbe, T. Oashi, K. Tsukamoto, Y. Nishioka, M. Matsuura, T. Eimori, M. Inuishi, I. Miyanaga, M. Nakamura, T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya, M. Ogura
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引用次数: 5

Abstract

We have integrated a high speed and high density 6T-SRAM cell (0.998 /spl mu/m/sup 2/) for system-on-a-chip (SOC) using enhanced 100 nm CMOS logic technology. This is achieved by a systematic integration methodology, which includes high-NA ArF lithography, optimized optical proximity correction (OPC) CAD, narrow well isolation, poly-buffered shallow trench isolation (STI), offset spacer transistor, and 9-level Cu interconnect and low-k dielectric technologies with the lithographically scalable SRAM cell design.
Sub-1 /spl mu/m/sup /高密度嵌入式SRAM技术,适用于100nm代SOC及以后
我们采用增强型100纳米CMOS逻辑技术集成了用于片上系统(SOC)的高速高密度6T-SRAM单元(0.998 /spl mu/m/sup 2/)。这是通过系统集成方法实现的,其中包括高na ArF光刻、优化的光学接近校正(OPC) CAD、窄井隔离、多缓冲浅沟槽隔离(STI)、偏移间隔晶体管、9级Cu互连和低k介电技术,以及光刻可扩展的SRAM单元设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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