K. Tomita, K. Hashimoto, T. Inbe, T. Oashi, K. Tsukamoto, Y. Nishioka, M. Matsuura, T. Eimori, M. Inuishi, I. Miyanaga, M. Nakamura, T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya, M. Ogura
{"title":"Sub-1 /spl mu/m/sup 2/ high density embedded SRAM technologies for 100 nm generation SOC and beyond","authors":"K. Tomita, K. Hashimoto, T. Inbe, T. Oashi, K. Tsukamoto, Y. Nishioka, M. Matsuura, T. Eimori, M. Inuishi, I. Miyanaga, M. Nakamura, T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya, M. Ogura","doi":"10.1109/VLSIT.2002.1015369","DOIUrl":null,"url":null,"abstract":"We have integrated a high speed and high density 6T-SRAM cell (0.998 /spl mu/m/sup 2/) for system-on-a-chip (SOC) using enhanced 100 nm CMOS logic technology. This is achieved by a systematic integration methodology, which includes high-NA ArF lithography, optimized optical proximity correction (OPC) CAD, narrow well isolation, poly-buffered shallow trench isolation (STI), offset spacer transistor, and 9-level Cu interconnect and low-k dielectric technologies with the lithographically scalable SRAM cell design.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1216 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015369","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
We have integrated a high speed and high density 6T-SRAM cell (0.998 /spl mu/m/sup 2/) for system-on-a-chip (SOC) using enhanced 100 nm CMOS logic technology. This is achieved by a systematic integration methodology, which includes high-NA ArF lithography, optimized optical proximity correction (OPC) CAD, narrow well isolation, poly-buffered shallow trench isolation (STI), offset spacer transistor, and 9-level Cu interconnect and low-k dielectric technologies with the lithographically scalable SRAM cell design.