1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献_第9页

Circuit technologies for 16Mb DRAMs 16Mb dram的电路技术

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157158

T. Mano, T. Matsumura, J. Yamada, J. Inoue, S. Nakajima, K. Minegishi, K. Miura, T. Matsuda, C. Hashimoto, H. Namatsu

{"title":"Circuit technologies for 16Mb DRAMs","authors":"T. Mano, T. Matsumura, J. Yamada, J. Inoue, S. Nakajima, K. Minegishi, K. Miura, T. Matsuda, C. Hashimoto, H. Namatsu","doi":"10.1109/ISSCC.1987.1157158","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157158","url":null,"abstract":"THIS PAPER WILL DESCRIBE circuit technologies not only necessary for submicron ULSl memories, but also for customized ULSIs including RAM blocks. Key circnlts proposed here are an on-chip error checking and correcting (ECC) circuit that induces little access penalty, and sense circuits suitable for fast datasensing at 3.3V operation. A 16Mb CMOS dynamic RAM incorporating a mainsub bitline structure and 4 . 9 p 2 IsolationMerged Vertical Capacitor (IVEC) cells has been designed and fabricated using a 0 . 7 m CMOS process as a test vehicle for these circuits. .As memory cell structures and fabrication processes become more complicated, the chip yield of megabit level DRAMs will be decreased by memory cell defects. It is difficult to overcome this problem using only conventional redundancy techniques. But the on-chip ECC circuit is useful in relieving hard errors caused by random cell defects. The circuit can also reduce alpha-particle induced soft error rates. However, previouslyproposed ECC circuitry' has an access penalty of 20ns, which prevents ECC circuits from being used on memory chips. To use an on-chip ECC circuit practically, the access penalty must be reduced.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126302008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

A 100ns 16-point CCD cosine transform processor 一个100ns 16点CCD余弦变换处理器

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157203

A. Chiang, P. Bennett, B. Kosicki, R. Mountain, G. Lincoln, J. Reinold

引用次数: 7

A CMOS 32b microprocessor with on-chip cache and transmission lookahead buffer 带有片上缓存和传输前瞻缓冲器的CMOS 32b微处理器

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157159

H. Kadota, J. Miyake, I. Okabayashi, T. Maeda, T. Okamoto, Y. Takagi, K. Kagawa, E. Ichinohe

{"title":"A CMOS 32b microprocessor with on-chip cache and transmission lookahead buffer","authors":"H. Kadota, J. Miyake, I. Okabayashi, T. Maeda, T. Okamoto, Y. Takagi, K. Kagawa, E. Ichinohe","doi":"10.1109/ISSCC.1987.1157159","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157159","url":null,"abstract":"THIS PAPER WILL DESCRIBE a singlechip CMOS 32b microprocessor supporting a smart memory hierarchy with on-chip Cache and TLB (Transmission Lookaside Buffer). The chip, containing 372k transistors, has been fabricated by using a double-metal layer CMOS technology with lpn design rule. It operates at 8011s machine cycle time and dissipates 1.7W. A high-speed address translation device is essential for the virtual memory system, and two full-associative TLBs for supervisor and user mode, respectively, are implemented for that purpose. Each device has 32 entries composed of a 28b data field (SRAM), a 29b tag field (CAM’) and replace control LRU (Least-Recently-Used) circuits: Figure 1. The pageoize can be varied from 512 to 4K bytes by 3b searchmasking of virtual address tag bits. The TLB access time is less than 22ns, with a half machine cycle (40ns) for a complete address translation, virtua2 to phys ica l , and carried out by an off-chip TLB in about 100ns. The replacement algorithm, LRU, is realized by a 32 x 5b matrix of magnitude comparator and counter. The tag field includes task-ID (TID) bits, in addition to virtual address bits and a valid bit. The task-ID bits are used for checking and taskassigned invalidation of entries. These functions serve for effective management and rapid context switching in a multi-tasking system. The LKbyte Instruction Cache relieves a I/O bottle-neck. A lpm-process technology permits the cache to be of large enough size for the multi-task environment. Its structure is two-way set associative, and 256 x 2 entries are composed of 26b tag fields (SRAM) and 32h data fields (SRAM): Figure 2. This Cache is virtually addressed, and its access time is less than 18ns in the hit case.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126419052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Single-chip NMOS AGC amplifiers for Gb/s lightwave systems 用于Gb/s光波系统的单片NMOS AGC放大器

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157135

R. Jindal, E. Hofstatter, O. Mizuhara

引用次数: 6

4Mb pseudo/virtually SRAM 4Mb伪/虚拟SRAM

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157228

S. Yoshioka, Y. Nagatomo, S. Takahashi, S. Miyamoto, M. Uesugi

引用次数: 11

An 8b 350MHz flash ADC 8b 350MHz闪存ADC

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157115

Y. Yoshii, M. Nakamura, K. Hirasawa, A. Kayanuma, K. Asano

引用次数: 7

Analog CMOS filter with full digital programmability 模拟CMOS滤波器与全数字可编程性

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157172

D. Vallancourt, Y. Tsividis

引用次数: 3

Scan path testing of a multichip computer 多芯片计算机扫描路径测试

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157190

R. Schuchard, D. Weiss

引用次数: 5

Two CMOS 0.5µm 32b digital macros 两个CMOS 0.5µm 32b数字宏

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157139

Chih-Liang Chen, Li-Kong Wang, A. Edenfeld, P. Nixon

引用次数: 0

Signal processors for isolated word recognition 用于孤立词识别的信号处理器

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157136

A. Yamaguchi, H. Shigehara, K. Sato, H. Iseki, H. Sekiguchi, J. Tsunoda, M. Koyama, T. Suzuki, T. Ishikawa, H. Chimoto, N. Sugi

引用次数: 0