Circuit technologies for 16Mb DRAMs

THIS PAPER WILL DESCRIBE circuit technologies not only necessary for submicron ULSl memories, but also for customized ULSIs including RAM blocks. Key circnlts proposed here are an on-chip error checking and correcting (ECC) circuit that induces little access penalty, and sense circuits suitable for fast datasensing at 3.3V operation. A 16Mb CMOS dynamic RAM incorporating a mainsub bitline structure and 4 . 9 p 2 IsolationMerged Vertical Capacitor (IVEC) cells has been designed and fabricated using a 0 . 7 m CMOS process as a test vehicle for these circuits. .As memory cell structures and fabrication processes become more complicated, the chip yield of megabit level DRAMs will be decreased by memory cell defects. It is difficult to overcome this problem using only conventional redundancy techniques. But the on-chip ECC circuit is useful in relieving hard errors caused by random cell defects. The circuit can also reduce alpha-particle induced soft error rates. However, previouslyproposed ECC circuitry' has an access penalty of 20ns, which prevents ECC circuits from being used on memory chips. To use an on-chip ECC circuit practically, the access penalty must be reduced.