1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

{"title":"A 512 × 512 element PtSi Schottky-barrier infrared image sensor","authors":"M. Kimata, M. Denda, N. Yutani, S. Iwade, N. Tsubouchi","doi":"10.1109/ISSCC.1987.1157233","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157233","url":null,"abstract":"An image sensor for thermal imaging in the3-5μm infrared band will be discussed. Device has a pixel size of26×20μm and a fill factor of 39% achieved by use of charge sweep vertical readout registers.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134350500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A CMOS chip pair for digital TV","authors":"S. Suzuki, K. Kawai, K. Muramatsu, T. Makino, S. Saji","doi":"10.1109/ISSCC.1987.1157223","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157223","url":null,"abstract":"A two-chip digital TV with the potential for 650 horizontal lines of resolution and implemented with 195 K transistors has been described. Both are fabricated in 1.5-/spl mu/m double-metal CMOS technology and assembled in plastic packages. The video processor with a 2 H one-transistor cell dynamic RAM line memory contains 140 K transistors in a 62-mm/SUP 2/ chip, operates up to 50 MHz, and dissipates 250 mW at 14.3 MHz. The synchronous processor dissipates 110 mW at 14.3 MHz.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"447 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123629382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A two-million moves/sec CMOS single chip chess move generator","authors":"Feng-hsiung Hsu","doi":"10.1109/ISSCC.1987.1157189","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157189","url":null,"abstract":"A 36K transistor, 3μm CMOS chip capable of generating 2 million chess moves/s will be detailed. Die size is 6.8×6.9mm.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125087770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An oversampling ADC macrocell with rail-to-rail input voltage capability","authors":"A. Yukawa, K. Nakayama, Y. Kawakami, K. Hinooka, Y. Mizukami","doi":"10.1109/ISSCC.1987.1157154","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157154","url":null,"abstract":"A 14b fully differential oversampling analog-to-digital converter that has 0.01% harmonic distortion and samples at 1MHz and additionally has rail-to-rail input voltage capability, will be presented. The macrocell has been fabricated in 1.5μm CMOS technology: die size is 1.5×0.8mm.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132065968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 60ns 4Mb DRAM in a 300mil DIP","authors":"T. Sumi, T. Taniguchi, M. Kishimoto, H. Hirano, H. Kuriyama, T. Nishimoto, H. Oishi, S. Tetakawa","doi":"10.1109/ISSCC.1987.1157106","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157106","url":null,"abstract":"THIS PAPER WILL DESCRIBE A 4Mb CMOS DRAM with a 60ns RAS access time and 4.54mm x 1.4.78mm (67.1mm2) chip area assembled in a 300mil dual-in-line plastic package. The RAM has been fabricated in a twin-tub CMOS process technology with double-poly, single-polycide and single-metal using a 0 . 8 ~ design rule. One of the key technologies to program in developing a 4Mb DRAM in a 300mil DIP is to produce stable small-size memory cells free from leakage current between adjacent cells. The leakage current inherent to the trench cell can be reduced by the adoption of trenches embedded in a P-well’ . Nonetheless, in a scaled DR.4M with deeptrench capacitors, leakage is likely to occur at the bottom of the trenches, because P-well concentration there is lower than at the surface’. A structural trench memory cell has been developed to overcome this problem. Figure 1 shows the cross-sectional view of the cell. Arsenic was doped at the side and bottom of the trench to form N-type regions preventing the memory cell capacitance decrease. Also, Boron was doped to form a Hi-C structure. This trench capacitor cell suppressed the leakage current between the adjacent cells of small spacing even at Vcc = 7V; it was possible to produce a 1.74,pm x 4 . 6 ~ ( 8 . 0 ~ 2 ) memory cell with a 40fF capacitance and a 4 p trench depth. The P-well concentration has been optimized for submicron N-channel transistor characteristics independently of the leakage problem. Table 1 summarizes the process parameters. Figure 2 shows the bitline and sensing circuits schematic. In a 4Mb DRAM the high-speed voltage bumping problem becomes more serious, and the conventional % Vcc cell plate method cannot eliminate this problem. The solution was found in circuits with a bitline precharge voltage (VBL) and a cell plate voltage (Vcp) set at the same voltage of approximately 2.3V, its dependence on weak Vcc. As a result, readout voltage loss due to Vcc bumping was reduced. One bitline is connected to 128 memoiy cells, 1 dummy cell and 1 redundancy cell. The dummy cell has the same capacitance as the memory cell __","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123164512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 35ns 1Mb CMOS SRAM","authors":"T. Komatsu, N. Okazaki, T. Nishihara, S. Kayama, N. Hoshi, J. Aaoyama, T. Shimada","doi":"10.1109/ISSCC.1987.1157110","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157110","url":null,"abstract":"A 128×8b CMOS SRAM with TTL input/output levels will be presented. The SRAM has been fabricated in a 1.0μm double-poly silicon double-metal CMOS technology Chip size is 8×13.65mm. Typical standby current is 5μA with 100mW dissipatlon at 10MHz. Noise immunity has been achieved from a dual threshold level data transfer.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115768811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 128K flash EEPROM using double polysilicon technology","authors":"G. Samachisa, C. Su, Y. Kao, G. Smarandoiu, T. Wong, C. Hu","doi":"10.1109/ISSCC.1987.1157210","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157210","url":null,"abstract":"An EEPROM with a 43μm2cell containing an integral select transistor will be reported. The chip features 140ns access time, 1ms/byte program time, 1s chip erase time and 1000 cycle endurance. Yields of the 4.6×3.4mm chip in a 2.5μm NMOS process are comparable to those of an EPROM.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121061211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Session 6 keynote address","authors":"R. Brodersen","doi":"10.1109/ISSCC.1987.1157162","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157162","url":null,"abstract":"The designer's ability to create new compact memory storage cells and dense layouts had served as a goal of the industry until recently, when new challenges began to appear. Today, the focus is on narrower market segments, where the profit margins can be significant, without requiring the lowest manufacturing costs. Up graded circuits in this new design era include those used in telecommunications, analog/digital interfaces and other application specific functions. Designer skills needed today are dramatically different today and will continue to change with changing technologies. The value of the chip is now in the implemented algorithms and architectures, and on the time to market. The answer to this need has been to use such techniques, as gate arrays and standard cell designs: two approaches that almost eliminate IC designers from the design process. The traditional designer's contribution must evolve into one that is primarily centered on determining new applications for ICs and new architectures that will make these applications possible. In circuits of 10's of thousands of transistors or larger, it is no longer rational to perform significant optimization at the transistor level, because architectural decisions can have considerably more impact. We have seen this in performance achieved by RISC microprocessors, and by recently developed image processing circuits performing hundreds of millions of operations/sec. The problem of enormous design complexity has frequently been attacked by the inefficient application of more manpower, rather than by use of efficient software tools. These tools should not replace the designer, rather they should relieve him of documentation and other mundane tasks. He can contribute and introduce innovations at the applications and architectural levels. However, the designer must be comfortable with software development, because only he will know what tools are required for unburdening him of the details, while leaving him in control of the design process. Enter - a new methodology- the reorganization of the traditional centralized CAD group and separate design groups into a more homogeneous mix of designers and tool developers. Relieving the designer of low-level tasks, permitting him to focus on identifying new applications, will require a greater systems level of orientation and the increasing use of diversified talent. The IC designer will become more of a facilitator between those who have applications and those who provide the circuit implementation. Also, the integration of analog circuit functions is becoming increasingly critical for many applications such as telecommunications. The design style used is now in the process of undergoing a major upheaval. The traditional techniques based on precision components are being replaced by techniques that are more compatible with the integration of systems on a chip. In summary, IC design of the future must be carefully reassessed.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116119497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 300MHz bipolar-CMOS video shift register with FIFO","authors":"P. Yeung, R. Shergill, Ta-Ming Wang, P. Tucci","doi":"10.1109/ISSCC.1987.1157121","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157121","url":null,"abstract":"A 16b video register containing a 4W ×16b FIFO, fabricated in a bipolar CMOS process will be described. The chip (19,500 sq mil) attains a serial data rate of 300MHz and a parallel date rate of 20MHz with a supply current of 130mA.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117041669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 4K GaAs SRAM with 1ns access time","authors":"H. Tanaka, H. Yamashita, N. Masuda, N. Matsunaga, M. Miyazaki, H. Yanazawa, A. Masaki, N. Hashimoto","doi":"10.1109/ISSCC.1987.1157229","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157229","url":null,"abstract":"An SRAM fabricated in 0.7μm gate Length FETs and employing current sensing will be presented. The discussion will include means to control thermal breakdown and an internal circuit to provide an ECL reference A 3.7×4.7mm die dissipates 1.6W.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"327 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124613304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}