A 35ns 1Mb CMOS SRAM

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157110

T. Komatsu, N. Okazaki, T. Nishihara, S. Kayama, N. Hoshi, J. Aaoyama, T. Shimada

引用次数: 6

Abstract

A 128×8b CMOS SRAM with TTL input/output levels will be presented. The SRAM has been fabricated in a 1.0μm double-poly silicon double-metal CMOS technology Chip size is 8×13.65mm. Typical standby current is 5μA with 100mW dissipatlon at 10MHz. Noise immunity has been achieved from a dual threshold level data transfer.

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一个35ns 1Mb CMOS SRAM

将介绍一种具有TTL输入/输出电平的128×8b CMOS SRAM。该SRAM采用1.0μm双多晶硅双金属CMOS技术制造，芯片尺寸为8×13.65mm。典型的待机电流为5μA, 10MHz时损耗为100mW。通过双阈值级数据传输实现了噪声抗扰性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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