A CMOS chip pair for digital TV

Abstract

A two-chip digital TV with the potential for 650 horizontal lines of resolution and implemented with 195 K transistors has been described. Both are fabricated in 1.5-/spl mu/m double-metal CMOS technology and assembled in plastic packages. The video processor with a 2 H one-transistor cell dynamic RAM line memory contains 140 K transistors in a 62-mm/SUP 2/ chip, operates up to 50 MHz, and dissipates 250 mW at 14.3 MHz. The synchronous processor dissipates 110 mW at 14.3 MHz.