用于数字电视的CMOS芯片对

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1987-10-01 DOI:10.1109/ISSCC.1987.1157223

S. Suzuki, K. Kawai, K. Muramatsu, T. Makino, S. Saji

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引用次数: 3

摘要

描述了一种具有650水平线分辨率和195k晶体管的双芯片数字电视。两者均采用1.5-/spl μ m双金属CMOS技术制造，并在塑料封装中组装。具有2 H单晶体管单元动态RAM线存储器的视频处理器在62毫米/SUP 2/芯片中包含140 K晶体管，工作频率高达50 MHz，在14.3 MHz时耗散250 mW。同步处理器在14.3 MHz时耗散110 mW。

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A CMOS chip pair for digital TV

A two-chip digital TV with the potential for 650 horizontal lines of resolution and implemented with 195 K transistors has been described. Both are fabricated in 1.5-/spl mu/m double-metal CMOS technology and assembled in plastic packages. The video processor with a 2 H one-transistor cell dynamic RAM line memory contains 140 K transistors in a 62-mm/SUP 2/ chip, operates up to 50 MHz, and dissipates 250 mW at 14.3 MHz. The synchronous processor dissipates 110 mW at 14.3 MHz.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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