A 60ns 4Mb DRAM in a 300mil DIP

Abstract

THIS PAPER WILL DESCRIBE A 4Mb CMOS DRAM with a 60ns RAS access time and 4.54mm x 1.4.78mm (67.1mm2) chip area assembled in a 300mil dual-in-line plastic package. The RAM has been fabricated in a twin-tub CMOS process technology with double-poly, single-polycide and single-metal using a 0 . 8 ~ design rule. One of the key technologies to program in developing a 4Mb DRAM in a 300mil DIP is to produce stable small-size memory cells free from leakage current between adjacent cells. The leakage current inherent to the trench cell can be reduced by the adoption of trenches embedded in a P-well’ . Nonetheless, in a scaled DR.4M with deeptrench capacitors, leakage is likely to occur at the bottom of the trenches, because P-well concentration there is lower than at the surface’. A structural trench memory cell has been developed to overcome this problem. Figure 1 shows the cross-sectional view of the cell. Arsenic was doped at the side and bottom of the trench to form N-type regions preventing the memory cell capacitance decrease. Also, Boron was doped to form a Hi-C structure. This trench capacitor cell suppressed the leakage current between the adjacent cells of small spacing even at Vcc = 7V; it was possible to produce a 1.74,pm x 4 . 6 ~ ( 8 . 0 ~ 2 ) memory cell with a 40fF capacitance and a 4 p trench depth. The P-well concentration has been optimized for submicron N-channel transistor characteristics independently of the leakage problem. Table 1 summarizes the process parameters. Figure 2 shows the bitline and sensing circuits schematic. In a 4Mb DRAM the high-speed voltage bumping problem becomes more serious, and the conventional % Vcc cell plate method cannot eliminate this problem. The solution was found in circuits with a bitline precharge voltage (VBL) and a cell plate voltage (Vcp) set at the same voltage of approximately 2.3V, its dependence on weak Vcc. As a result, readout voltage loss due to Vcc bumping was reduced. One bitline is connected to 128 memoiy cells, 1 dummy cell and 1 redundancy cell. The dummy cell has the same capacitance as the memory cell __