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1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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Switched-capacitor voltage converter in bipolar technology with 100mA output current 双极技术的开关电容电压变换器，输出电流100mA
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157099
D. O’Neill
{"title":"Switched-capacitor voltage converter in bipolar technology with 100mA output current","authors":"D. O’Neill","doi":"10.1109/ISSCC.1987.1157099","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157099","url":null,"abstract":"A voltage converter with 100mA output capability over a 3.5 - 15V range will be reported. Voltage loss is less than 1.2V at 100mA. A bipolar process has been used to obtain switch transistors with low on resistance and high emitter-base breakdown voltage. An adaptive non-overlapping switch drive optimizes efficiency.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114167195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
30MHz compiled chip set for graphics computations 用于图形计算的30MHz编译芯片组
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157199
S. Noujaim, R. Hartley, H. Cline, R. Jerdonek, S. Ludke
{"title":"30MHz compiled chip set for graphics computations","authors":"S. Noujaim, R. Hartley, H. Cline, R. Jerdonek, S. Ludke","doi":"10.1109/ISSCC.1987.1157199","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157199","url":null,"abstract":"A 1.25μm CMOS chip that has attained a device density of 1500 transistors/mm2, using a silicon compiler for design, will be described. The bit-slice elements of the chip communicate serially to implement a pipeline with a throughput of 50 million multiply/accumulates/s at a 30MHz clock rate.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122038986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 42ns 1Mb CMOS SRAM 42ns 1Mb CMOS SRAM
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157184
O. Minato, T. Sasaki, S. Honjo, K. Ishibashi, Y. Sasaki, N. Moriwaki, K. Nishimura, Y. Sakai, S. Meguro, M. Tsunematsu, T. Masuhara
{"title":"A 42ns 1Mb CMOS SRAM","authors":"O. Minato, T. Sasaki, S. Honjo, K. Ishibashi, Y. Sasaki, N. Moriwaki, K. Nishimura, Y. Sakai, S. Meguro, M. Tsunematsu, T. Masuhara","doi":"10.1109/ISSCC.1987.1157184","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157184","url":null,"abstract":"A 128KW×8b RAM with address access time of 42ns and power dissipation of 200mW at 10MHz will be presented. Cell size of 45μm2has been achieved by using polysilicon technology and 0.8μm MOS transistors.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127101974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A line-address CCD image sensor 线寻址CCD图像传感器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157119
T. Yamada, K. Ikeda, N. Suzuki
{"title":"A line-address CCD image sensor","authors":"T. Yamada, K. Ikeda, N. Suzuki","doi":"10.1109/ISSCC.1987.1157119","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157119","url":null,"abstract":"This paper will describe a 1/2\" format 570(H)×495(V) pixel line-address CCD image sensor. The cell size is 11.5(H)×10(V)μm2. The sensor achieves a 38% fill factor: used are interlined multiphase vertical CCD registers.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121178500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An 80ns address-date multiplex 1mb CMOS EPROM 80ns地址日期多路1mb CMOS EPROM
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157235
M. Yoshida, T. Akaogi, M. Higuchi, K. Shirai, I. Tanaka
{"title":"An 80ns address-date multiplex 1mb CMOS EPROM","authors":"M. Yoshida, T. Akaogi, M. Higuchi, K. Shirai, I. Tanaka","doi":"10.1109/ISSCC.1987.1157235","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157235","url":null,"abstract":"This report will cover an EPROM organized as 64K×16b. Precharging techniques achieved an access time of 80ns Light-shielded cells control switching of redundant word lines.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"539 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116395518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 70ns 4Mb DRAM in a 300mil DIP using 4-layer poly 一个70ns 4Mb DRAM在一个300mil DIP使用4层聚
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157161
H. Mochizuki, Y. Kodama, T. Nakano, T. Ema, T. Yabu
{"title":"A 70ns 4Mb DRAM in a 300mil DIP using 4-layer poly","authors":"H. Mochizuki, Y. Kodama, T. Nakano, T. Ema, T. Yabu","doi":"10.1109/ISSCC.1987.1157161","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157161","url":null,"abstract":"divided into four 1Mb blocks which have its own clock drivers. Because only one of them operates in each read or write cycle, the RAM dissipates less than 40mA (typical). Each lhlb block has two arrays of column decoders with sense amplifiers on both sides of them. Figure 2 shows sense amplifier circuit. Isolation transistors are inserted between bitlines and an N-channel sense amplifier to isolate noises from the bit lines and to amplify a minute signal correctly. P-channel cross-coupled transistors are arranged outside the isolation transistors to restore a bit line and a cell to full VCC level.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130651101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Directions in smart power ICs 智能电源集成电路研究方向
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157078
D. Monticelli
{"title":"Directions in smart power ICs","authors":"D. Monticelli","doi":"10.1109/ISSCC.1987.1157078","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157078","url":null,"abstract":"A new breed of VLSI is emerging: dies containing large power devices in combination with control circuitry. The smart power IC converts the small signal output of a system to drive a load, often conducting many amperes and standing off hundreds of volts in so doing. Present ICs involve such functions as protection, status or pulse width control and are constantly evolving towards expanding sophistication. The panel will explore the future of smart power in all of its aspects. The nature of the power device(s) and the extent of its intelligence will be assessed in light of new fabrication processes and consider MOS versus bipolar digital versus analog, monolithic versus multiple die solutions, standard versus custom and the challenge of packaging.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128777835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An analog expert design system 模拟专家设计系统
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157180
M. Degrauwe, O. Nys, E. Vittoz, E. Dijkstra, J. Rijmenants, S. Bitz, S. Cserveny, J. Sánchez
{"title":"An analog expert design system","authors":"M. Degrauwe, O. Nys, E. Vittoz, E. Dijkstra, J. Rijmenants, S. Bitz, S. Cserveny, J. Sánchez","doi":"10.1109/ISSCC.1987.1157180","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157180","url":null,"abstract":"A CMOS analog design expert system able to generate device dimensions and bias current for a library of transconductance and operational amplifiers, voltage references, quartz oscillators, low noise BiMOS amplifiers and oversampling ADC, will be reported.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131002355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A VLSI 128-channel data link control 一个超大规模集成电路128通道数据链路控制
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157156
P. Chao, G. Cyr, T. Hiller, R. King, R. Wilson
{"title":"A VLSI 128-channel data link control","authors":"P. Chao, G. Cyr, T. Hiller, R. King, R. Wilson","doi":"10.1109/ISSCC.1987.1157156","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157156","url":null,"abstract":"A controller with a 160K transistor automatically extracted from a behavorial description and fabricated in 1μm CMOS will be described. The chip is 367×390 mils, attaining a device density of 0.9mil2per transistor and dissipates 600mW at a clock rate of 8MHz.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124046088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 130K-gate mainframe chip set 130k门主机芯片组
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157144
K. Ikeda, A. Yamagiwa, K. Ikuzaki, M. Fujita, A. Masaki, M. Asano
{"title":"A 130K-gate mainframe chip set","authors":"K. Ikeda, A. Yamagiwa, K. Ikuzaki, M. Fujita, A. Masaki, M. Asano","doi":"10.1109/ISSCC.1987.1157144","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157144","url":null,"abstract":"This presentation will cover a mainframe chip set using three VLSIs containing 542K transistors, employing a rapid turn-around standard cell design methodology. Employing 1.3μm buld processing and controlled by an 8-phase clocking system, the chip operates with a cycle time of less than 60ns and an average propagation delay of less than 0.9ns.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123414351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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