O. Minato, T. Sasaki, S. Honjo, K. Ishibashi, Y. Sasaki, N. Moriwaki, K. Nishimura, Y. Sakai, S. Meguro, M. Tsunematsu, T. Masuhara
{"title":"A 42ns 1Mb CMOS SRAM","authors":"O. Minato, T. Sasaki, S. Honjo, K. Ishibashi, Y. Sasaki, N. Moriwaki, K. Nishimura, Y. Sakai, S. Meguro, M. Tsunematsu, T. Masuhara","doi":"10.1109/ISSCC.1987.1157184","DOIUrl":null,"url":null,"abstract":"A 128KW×8b RAM with address access time of 42ns and power dissipation of 200mW at 10MHz will be presented. Cell size of 45μm2has been achieved by using polysilicon technology and 0.8μm MOS transistors.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157184","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A 128KW×8b RAM with address access time of 42ns and power dissipation of 200mW at 10MHz will be presented. Cell size of 45μm2has been achieved by using polysilicon technology and 0.8μm MOS transistors.