A 130K-gate mainframe chip set

Abstract

This presentation will cover a mainframe chip set using three VLSIs containing 542K transistors, employing a rapid turn-around standard cell design methodology. Employing 1.3μm buld processing and controlled by an 8-phase clocking system, the chip operates with a cycle time of less than 60ns and an average propagation delay of less than 0.9ns.