A 70ns 4Mb DRAM in a 300mil DIP using 4-layer poly

divided into four 1Mb blocks which have its own clock drivers. Because only one of them operates in each read or write cycle, the RAM dissipates less than 40mA (typical). Each lhlb block has two arrays of column decoders with sense amplifiers on both sides of them. Figure 2 shows sense amplifier circuit. Isolation transistors are inserted between bitlines and an N-channel sense amplifier to isolate noises from the bit lines and to amplify a minute signal correctly. P-channel cross-coupled transistors are arranged outside the isolation transistors to restore a bit line and a cell to full VCC level.