130k门主机芯片组

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157144

K. Ikeda, A. Yamagiwa, K. Ikuzaki, M. Fujita, A. Masaki, M. Asano

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引用次数: 4

摘要

本报告将介绍使用三个包含542K晶体管的vlsi的大型主机芯片组，采用快速周转标准单元设计方法。该芯片采用1.3μm结构工艺，采用8相时钟系统控制，周期时间小于60ns，平均传播延迟小于0.9ns。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 130K-gate mainframe chip set

This presentation will cover a mainframe chip set using three VLSIs containing 542K transistors, employing a rapid turn-around standard cell design methodology. Employing 1.3μm buld processing and controlled by an 8-phase clocking system, the chip operates with a cycle time of less than 60ns and an average propagation delay of less than 0.9ns.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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