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1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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A 160Kb/s transceiver for digital subscriber loop 用于数字用户环路的160Kb/s收发器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157191
D. Sallaerts, R. Dierckx, M. Rahier
{"title":"A 160Kb/s transceiver for digital subscriber loop","authors":"D. Sallaerts, R. Dierckx, M. Rahier","doi":"10.1109/ISSCC.1987.1157191","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157191","url":null,"abstract":"This report will describe the implementation of a transceiver based on echo-cancelling, block code and single baud sampling techniques. A BER lower than 10-7has been obtained on loops up to 8km. The digital implementation in 2μm CMOS has resulted in a 45mm2chip area.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126669893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 90ns 4Mb DRAM in a 300 mil DIP 一个90ns 4Mb的DRAM在一个300mil DIP
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157143
K. Mashiko, M. Nagatomo, K. Arimoto, Y. Matsuda, K. Furutani, T. Matsukawa, T. Yoshihara, T. Nakano
{"title":"A 90ns 4Mb DRAM in a 300 mil DIP","authors":"K. Mashiko, M. Nagatomo, K. Arimoto, Y. Matsuda, K. Furutani, T. Matsukawa, T. Yoshihara, T. Nakano","doi":"10.1109/ISSCC.1987.1157143","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157143","url":null,"abstract":"A 4Mb DRAM employing a folded-bitline adaptive sidewall - isolated capacitance cell with 2μm deep trenches, a 72.3mm2chip size and 90ns access time will be described. Also incorporated are full bonding options for 4Mb×1 or 1Mb×4 organizations and for static column or page-mode operation.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126879304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 400mm long linear X-ray sensitive image sensor 一个400mm长的线性x射线敏感图像传感器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157125
J. Sevenhans, C. Claeys, I. Debusschere, G. Declerck
{"title":"A 400mm long linear X-ray sensitive image sensor","authors":"J. Sevenhans, C. Claeys, I. Debusschere, G. Declerck","doi":"10.1109/ISSCC.1987.1157125","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157125","url":null,"abstract":"A solid-state X-ray sensitive diode array with on-chip serial readout circuitry will be reported. The sensor consists of 128 diodes on a pitch of 400μm. Die size is 50×4mm. Device operates at a 1MHz pixel rate and achieves a sensitivity of 2.3nA/mm2for a tungsten tube at 100KeV and 9mA cathode current.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124325105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 256K CMOS SRAM with internal refresh 带有内部刷新的256K CMOS SRAM
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157079
S. Hanamura, O. Minato, T. Masuhara, Y. Sakai, T. Yamanaka, N. Moriwaki, F. Kojima
{"title":"A 256K CMOS SRAM with internal refresh","authors":"S. Hanamura, O. Minato, T. Masuhara, Y. Sakai, T. Yamanaka, N. Moriwaki, F. Kojima","doi":"10.1109/ISSCC.1987.1157079","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157079","url":null,"abstract":"A four-transistor switched-capacitor load SRAM employing 0.8μm CMOS technology with a cell size of 39.2μm2will be reported. The approach makes it possible to access without time-loss for internal refresh. Access time is 43ns and standby power is 3.3μW.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126354443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 48ps ECL in a self-aligned bipolar technology 自对准双极技术中的48ps ECL
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157152
K. Washio, T. Nakamura, K. Nakazato, T. Hayashida
{"title":"A 48ps ECL in a self-aligned bipolar technology","authors":"K. Washio, T. Nakamura, K. Nakazato, T. Hayashida","doi":"10.1109/ISSCC.1987.1157152","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157152","url":null,"abstract":"A polysilicon edge base contact bipolar technology with a gate array of 48ps and a mixed ECL-I2L frequency divider operating at 10GHz will be described.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125754792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A 32b CMOS microprocessor with on-chip instruction and data caching and memory management 具有片上指令、数据缓存和内存管理的32b CMOS微处理器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157147
D. Archer, D. Deverell, F. Fox, P. Gronowski, A. Jain, M. Leary, A. Olesin, S. D. Persels, P. Rubinfeld, D. Schumacher, B. Supnik, T. Thrush
{"title":"A 32b CMOS microprocessor with on-chip instruction and data caching and memory management","authors":"D. Archer, D. Deverell, F. Fox, P. Gronowski, A. Jain, M. Leary, A. Olesin, S. D. Persels, P. Rubinfeld, D. Schumacher, B. Supnik, T. Thrush","doi":"10.1109/ISSCC.1987.1157147","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157147","url":null,"abstract":"A processor implemented with 180K transistors in 2μm CMOS technology will be presented. The chip size is 9.7mm × 9.4mm, and the instruction set is compatible with a minicomputer.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121796580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 19ns memory 19ns存储器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157127
A. Suzuki, S. Yamaguchi, H. Ito, N. Suzuki, T. Yabu
{"title":"A 19ns memory","authors":"A. Suzuki, S. Yamaguchi, H. Ito, N. Suzuki, T. Yabu","doi":"10.1109/ISSCC.1987.1157127","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157127","url":null,"abstract":"A CMOS memory for cache systems which includes 49K bits SRAM and about 3500 transistors for logic will be presented. The memory achieves access times of 19ns from address to hit and 9.5ns from tag to hit, using address transition detection.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130170542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 50ns DSP with parallel processing architecture 50ns DSP并行处理结构
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157130
K. Kaneko, T. Nakagawa, A. Kiuchi, Y. Hagiwara, H. Ueda, H. Matsushima, T. Akazawa, T. Satoh, J. Ishida
{"title":"A 50ns DSP with parallel processing architecture","authors":"K. Kaneko, T. Nakagawa, A. Kiuchi, Y. Hagiwara, H. Ueda, H. Matsushima, T. Akazawa, T. Satoh, J. Ishida","doi":"10.1109/ISSCC.1987.1157130","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157130","url":null,"abstract":"This report will cover a programmable DSP that avoids I/O bottlenecks through a two-level hierarchy of instructions. The IC contains 430K transistors on a 149mm2die.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134058635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
DRAM cell structures and technologies DRAM单元结构与技术
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157163
A. Shah
{"title":"DRAM cell structures and technologies","authors":"A. Shah","doi":"10.1109/ISSCC.1987.1157163","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157163","url":null,"abstract":"Over a dozen different cell structures and technologies have been proposed in the past few years to reduce DRAM cell size. Each of the proposals represents a tradeoff between process complexity, cell size and cell perfarmance. This panel will attempt to identify the advantages and disadvantages of these competing approaches and try to understand the trend in cell structures and technologies for the next generation of DRAMs.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXX 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131198797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An ECL gate array hardened against soft errors ECL门阵列对软错误进行了强化
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157091
M. Okabe, M. Tatsuki, K. Sakaue, T. Hirao, Y. Kuramitsu
{"title":"An ECL gate array hardened against soft errors","authors":"M. Okabe, M. Tatsuki, K. Sakaue, T. Hirao, Y. Kuramitsu","doi":"10.1109/ISSCC.1987.1157091","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157091","url":null,"abstract":"A 1.3μm gate array whose soft error rate is improved by a factor of 100 over a conventional design will be reported.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132430361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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