{"title":"A microprocessor with 2Kbytes EEPROM for data security applications","authors":"H. Nakamura, T. Sawase, T. Kihara, K. Matsubara","doi":"10.1109/ISSCC.1987.1157085","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157085","url":null,"abstract":"This paper will cover a chip for filing and controlling personal data files. The 5.6×5.7mm IC has been fabricated in 2μm CMOS, and uses ROM self-comparison and EEPROM security check circuits.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124564140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A CMOS associative memory chip based on neural networks","authors":"H. Graf, P. de Vegvar","doi":"10.1109/ISSCC.1987.1157193","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157193","url":null,"abstract":"This report will describe a chip containing 54 amplifiers, 6K SRAM and programmable interconnections, that has been used to implement an algorithm based on biological neural networks. The 75K transistor chip was fabricated in 25μm CMOS, measures 6.7×6.7mm and dissipates 500mW. Ten vectors stored in the memory may be recalled within 500ns.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114569102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Coffman, D. Boyd, D. Dolby, M. Gill, S. Kady, R. Lahiry, Sun Lin, D. McEkroy, A. Mitchell, J. Paterson, J. Schreck, P. Shah, F. Takeda
{"title":"A 1Mb CMOS EPROM with a 13.5µm2cell","authors":"T. Coffman, D. Boyd, D. Dolby, M. Gill, S. Kady, R. Lahiry, Sun Lin, D. McEkroy, A. Mitchell, J. Paterson, J. Schreck, P. Shah, F. Takeda","doi":"10.1109/ISSCC.1987.1157140","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157140","url":null,"abstract":"A 64K×16b EPROM with an access time of 159ns will be reported. Buried diffusion reduces the number of array contacts to one every 16b. The circuit includes eight test features and requires a program time of 65ns for the complete array.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114676996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takayuki Ohtani, Kazuhiko Hashirnoto, M. Matsui, Jun-ichi Tsujimoto, H. Iwai, Mitsuchika Saitoh, H. Shibata, Hisayo Sasaki, Mitsuo Isobe, J. Matsunaga, Tetsuya lizuka
{"title":"A 25ns 1Mb CMOS SRAM","authors":"Takayuki Ohtani, Kazuhiko Hashirnoto, M. Matsui, Jun-ichi Tsujimoto, H. Iwai, Mitsuchika Saitoh, H. Shibata, Hisayo Sasaki, Mitsuo Isobe, J. Matsunaga, Tetsuya lizuka","doi":"10.1109/ISSCC.1987.1157219","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157219","url":null,"abstract":"HIGH-SPEED OPERATION and low-power consumption are crucial requirements for the new generation high density SR.4kIs. This paper will describe development of a Mb chip with a typical address access time of 25ns and typical operating current of 15mA. Desired performance has been realized by bit-line circuitry (LOAF bit line), a 2-stage sense amplifier utilizing renewed double word-line structure, address transition detection techniques and a 0 .8m CMOS process with double-level polysilicon and double-level aluminum layers.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1998 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128251295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A character string search processor","authors":"H. Yamada, M. Hirata, H. Nagai, K. Takahashi","doi":"10.1109/ISSCC.1987.1157142","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157142","url":null,"abstract":"This paper will describe an accelerator chip for rapid text retrieval, fabricated in a 1.6μm CMOS technology Concurrent comparison of 64 stored strings of variable length in 50ns has been demonstrated, for an input text stream of 10M characters/s.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127368683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 500V/µs 12b transimpedance amplifier","authors":"W. Palmer, B. Hilton","doi":"10.1109/ISSCC.1987.1157179","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157179","url":null,"abstract":"A current-to-voltage amplifier with ±10 V output capability, and a settling time of 120ns to 12b accuracy will be discussed. A 100MΩ transresistance, 20μV input offset voltage and 100nA input current were obtained in a junction isolated bipolar technology.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132168865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 256-element associative parallel processor","authors":"I. Jalowiechi, R. Lea","doi":"10.1109/ISSCC.1987.1157086","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157086","url":null,"abstract":"A 145K transistor, 2μm CMOS parallel processor capable of executing 262-million 8b additions/s will be detailed. Under the control of an external sequencer, the chip has been used to perform a 3×3 8b convolution in 95μs for image processing applications.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123785212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Akazawa, A. Iwata, T. Wakimoto, T. Kamato, H. Nakamura, H. Ikawa
{"title":"A 400MSPS 8b flash AD conversion LSI","authors":"Y. Akazawa, A. Iwata, T. Wakimoto, T. Kamato, H. Nakamura, H. Ikawa","doi":"10.1109/ISSCC.1987.1157082","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157082","url":null,"abstract":"This report will disclose a 18GHz fTbipolar technology which has been used to design a 400MSPS A-D converter with a 2.7W power consumption. The SNR is 40dB and a 100MHz input frequency results in a 10ps sampling jitter.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122520651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Hori, G. Kitsukawa, Y. Kawajiri, T. Watanabe, T. Kawahara, K. Itoh, Y. Kobayashi, M. Oohayashi, K. Asayama, T. Ikeda, H. Kawamoto
{"title":"An experimental 35ns 1Mb biCMOS DRAM","authors":"R. Hori, G. Kitsukawa, Y. Kawajiri, T. Watanabe, T. Kawahara, K. Itoh, Y. Kobayashi, M. Oohayashi, K. Asayama, T. Ikeda, H. Kawamoto","doi":"10.1109/ISSCC.1987.1157141","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157141","url":null,"abstract":"AN EXPERIMENTAL I Rlb bipolar CMOS (Hi-BiCMOS) DRAM with a typical access time of 35ns and typical power dissipation of 450mW at a 60ns cycle time, will be reported. The key to achieving high-speed DRAMs is to introduce high performance bipolar transistors, while maintaining high soft-error immunity, low-power dissipation and low-peak current, even at cycle times shorter than 100ns. Four developments are proposed to meet these requirements: a Hi-BiCMOS DRAM device structure', a high-speed bipolar circuitry combined with a highspeed memory array configuration, a BiCMOS clock driver suitable for an owchip voltage limiter and a current mirror circuit combined with a voltage limiter. Figure 1 shows a Hi-BiCMOS DRAM device structure with twin wells formed in a 1.5pm epitaxial layer. This structure realizes a high fT because the bipolar transistors used have an optimum emitter width of 3 p . In addition, the elimination of the P t buried layer results in a low threshold voltage sensitivity to the substrate bias for NMOSTs in the peripheral circuitry. The'se characteristics are essential for high-speed operation. The bipolar transistor emitters are formed concurrently with the sources and drains of the NMOST. Thus, the fabrication process is almost fully compatible with the conventional CMOS DKARiI; only three additional masking steps are required. The planar cell is formed just above the P+ buried layer to provide high soft error immunity.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122648786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A GaAs 1K SRAM with 2ns cycle time","authors":"B. Gabillard, C. Rocher, T. Ducourant, M. Prost","doi":"10.1109/ISSCC.1987.1157128","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157128","url":null,"abstract":"An ECL compatible SRAM that attains rise and fall times of 200ps with a power consumtpion of 210mW will be described. Word line clamping and data bus delay reduction allow control of the access time in spite of threshold voltage varation of 90mV.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114243602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}