周期时间为2ns的GaAs 1K SRAM

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157128

B. Gabillard, C. Rocher, T. Ducourant, M. Prost

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引用次数: 2

摘要

将描述一种ECL兼容的SRAM，其上升和下降时间为200ps，功耗为210mW。尽管阈值电压变化为90mV，但字线箝位和数据总线延迟减少允许控制访问时间。

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A GaAs 1K SRAM with 2ns cycle time

An ECL compatible SRAM that attains rise and fall times of 200ps with a power consumtpion of 210mW will be described. Word line clamping and data bus delay reduction allow control of the access time in spite of threshold voltage varation of 90mV.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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