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1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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A 300Mb/s clock recovery and data retiming system 300Mb/s时钟恢复和数据重定时系统
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157134
G. Andrews, D. Farley, S. Kravitz, A. Schelling, P. Davis, L. McAfee
{"title":"A 300Mb/s clock recovery and data retiming system","authors":"G. Andrews, D. Farley, S. Kravitz, A. Schelling, P. Davis, L. McAfee","doi":"10.1109/ISSCC.1987.1157134","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157134","url":null,"abstract":"A single bipolar chip housed with a Surface Acoustic Wave filter in a multi-cavity ceramic DIP to provide clock recovery and data retiming up to 300Mb/s will be discussed. Device accepts a jittered data input and provides a low jitter clock (<3°rms)and retimed data with 10% eye width closure on ECL balanced outputs.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123345301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 64K GaAs gate array 一个64K GaAs栅极阵列
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157131
T. Terada, Y. Ikawa, A. Kameyama, K. Kawakyu, T. Sasaki, Y. Kitaura, K. Ishida, K. Nishihori, N. Toyoda
{"title":"A 64K GaAs gate array","authors":"T. Terada, Y. Ikawa, A. Kameyama, K. Kawakyu, T. Sasaki, Y. Kitaura, K. Ishida, K. Nishihori, N. Toyoda","doi":"10.1109/ISSCC.1987.1157131","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157131","url":null,"abstract":"This paper will report on a gate array that employs Schottky diode capacitor-coupled logic to attain a noise margin of 400mV. At a power dissipation of 1mW%gate, the propagation delay was 284ps.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122724611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A processor for graph search algorithms 图形搜索算法的处理器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157098
S. Glinski, T. M. Lalumia, D. Cassiday, T. Koh, C. Gerveshi, G. Wilson, J. Kumar
{"title":"A processor for graph search algorithms","authors":"S. Glinski, T. M. Lalumia, D. Cassiday, T. Koh, C. Gerveshi, G. Wilson, J. Kumar","doi":"10.1109/ISSCC.1987.1157098","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157098","url":null,"abstract":"This report will describe a programmable signal processor with a pipelined arithemetic unit capable of 40 MIPs operation in graph search kernel operations. Thus a fivefold improvement in speech and image processing algorithms can be obtained over conventional architectures The chip was fabricated in a 1.5μm CMOS technology, occupies 43.4mm2and operates at 20MHz.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122867699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A monolithic line interface circuit for T1 terminals 用于T1端子的单片线路接口电路
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157076
K. Stern, N. Sooch, D. Knapp, M. Nix
{"title":"A monolithic line interface circuit for T1 terminals","authors":"K. Stern, N. Sooch, D. Knapp, M. Nix","doi":"10.1109/ISSCC.1987.1157076","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157076","url":null,"abstract":"The paper will cover an interface circuit capable of driving 25 ohm lines, that contains a pulse-shaping driver and a PLL for clock and data recovery. The circuit has been fabricated in 3μm CMOS.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129877638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 4OMHz programmable semi-systolic transversal fitter 4OMHz可编程半收缩横向滤波器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157074
T. Noll, S. Meier
{"title":"A 4OMHz programmable semi-systolic transversal fitter","authors":"T. Noll, S. Meier","doi":"10.1109/ISSCC.1987.1157074","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157074","url":null,"abstract":"This paper will report on a transversal filter architecture with programmable coefficients. A test chip of a 7 tap fitter with 10b data, 8b coefficients and a 40MHz sampling rate has been realized. The 38.5K transistors with a total chip area of 14.6mm2in a 1.5μ CMOS technology achieve a functional throughput rate-per chip area of4×10^{12}Hz times gates per cm2.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"02 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129676529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A single-chip functional tester 单片机功能测试仪
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157182
J. Miyamoto, M. Horowitz
{"title":"A single-chip functional tester","authors":"J. Miyamoto, M. Horowitz","doi":"10.1109/ISSCC.1987.1157182","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157182","url":null,"abstract":"The architecture of a 64.5K transistor chip that generates 192 test vectors and compares them witll data returned by a 16-pin device under test, will be described. It is implemented in 3μm CMOS, with a die size of 9.2×7.9mm. Dissipation is 300mW at a 10MHz clock rate.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130224588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Competing technologies for high-speed digital systems 高速数字系统的竞争技术
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157166
R. Stewart
{"title":"Competing technologies for high-speed digital systems","authors":"R. Stewart","doi":"10.1109/ISSCC.1987.1157166","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157166","url":null,"abstract":"Several new technologies, including sub-micron CMOS, SOI/ SMOS, BiCMOS GaAs and advanced bipolar ECL, are being developed for the super-fast ULSI digital system of the '90s. . . The panel will discuss whether the continued scaling of bulk CMOS will be adequate or whether a change over to technologies such as SOI or GaAs will be required . . . Meaningful measures for comparing these technologies will also be assessed.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127621909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 21ns 32K×8 CMOS SRAM with a selectively pumped P-well array 具有选择性泵浦p阱阵列的21ns 32K×8 CMOS SRAM
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157234
K. Wang, M. D. Bader, P. Voss, V. Soorholtz, R. Mauntel, H. Mendez, R. Kung
{"title":"A 21ns 32K×8 CMOS SRAM with a selectively pumped P-well array","authors":"K. Wang, M. D. Bader, P. Voss, V. Soorholtz, R. Mauntel, H. Mendez, R. Kung","doi":"10.1109/ISSCC.1987.1157234","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157234","url":null,"abstract":"A selectivity pumped P-well array used in a 32K×8 CMOS SRAM with a divided-word line block architecture to achieve a 21ns access time, will be described. The chip (6.83×8.97mm) was processed in a 1.2μm double-level metal, twin-well CMOS technology. Active power is 330mW at 22MHz.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122258087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Layout methods to reduce CMOS stuck-open faults and enhance testability 采用布局方法减少CMOS卡开故障，提高可测试性
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157176
S. Koeppe
{"title":"Layout methods to reduce CMOS stuck-open faults and enhance testability","authors":"S. Koeppe","doi":"10.1109/ISSCC.1987.1157176","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157176","url":null,"abstract":"CMOS layout rules that reduce the stuck-open faults by 30 to 40% and render the remaining detectagle with usual stuck-at test patterns, will be analyzed. The area penalty is less than 20%.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122309389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A modular design and test approach for a family of VLSI MPUs 一种VLSI系列微处理器的模块化设计与测试方法
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157227
D. Braune, A. Guerin, J. Lebrousse
{"title":"A modular design and test approach for a family of VLSI MPUs","authors":"D. Braune, A. Guerin, J. Lebrousse","doi":"10.1109/ISSCC.1987.1157227","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157227","url":null,"abstract":"Processors based on a commercial CPU integrated with supporting modules will be described. A handcrafted optimization of the core and semi-custom design of the on-chip modules will be detailed.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127202004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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