具有选择性泵浦p阱阵列的21ns 32K×8 CMOS SRAM

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157234

K. Wang, M. D. Bader, P. Voss, V. Soorholtz, R. Mauntel, H. Mendez, R. Kung

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引用次数: 2

摘要

本文将介绍一种用于32K×8 CMOS SRAM的选择性泵浦p阱阵列，该阵列具有分字线块结构，可实现21ns的访问时间。该芯片(6.83×8.97mm)采用1.2μm双层金属双孔CMOS工艺。22MHz有功功率为330mW。

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A 21ns 32K×8 CMOS SRAM with a selectively pumped P-well array

A selectivity pumped P-well array used in a 32K×8 CMOS SRAM with a divided-word line block architecture to achieve a 21ns access time, will be described. The chip (6.83×8.97mm) was processed in a 1.2μm double-level metal, twin-well CMOS technology. Active power is 330mW at 22MHz.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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