单片机功能测试仪

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157182

J. Miyamoto, M. Horowitz

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引用次数: 3

摘要

本文将描述64.5K晶体管芯片的架构，该芯片可生成192个测试向量，并将其与被测16针器件返回的数据进行比较。它在3μm CMOS中实现，芯片尺寸为9.2×7.9mm。在10MHz时钟速率下，功耗为300mW。

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A single-chip functional tester

The architecture of a 64.5K transistor chip that generates 192 test vectors and compares them witll data returned by a 16-pin device under test, will be described. It is implemented in 3μm CMOS, with a die size of 9.2×7.9mm. Dissipation is 300mW at a 10MHz clock rate.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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