A 300Mb/s clock recovery and data retiming system

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157134

G. Andrews, D. Farley, S. Kravitz, A. Schelling, P. Davis, L. McAfee

引用次数: 3

Abstract

A single bipolar chip housed with a Surface Acoustic Wave filter in a multi-cavity ceramic DIP to provide clock recovery and data retiming up to 300Mb/s will be discussed. Device accepts a jittered data input and provides a low jitter clock (<3°rms)and retimed data with 10% eye width closure on ECL balanced outputs.

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300Mb/s时钟恢复和数据重定时系统

将讨论在多腔陶瓷DIP中安装表面声波滤波器的单双极芯片，以提供高达300Mb/s的时钟恢复和数据重定时。设备接受抖动数据输入，并提供低抖动时钟(<3°rms)和在ECL平衡输出上具有10%眼宽关闭的重新定时数据。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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