S. Glinski, T. M. Lalumia, D. Cassiday, T. Koh, C. Gerveshi, G. Wilson, J. Kumar
{"title":"图形搜索算法的处理器","authors":"S. Glinski, T. M. Lalumia, D. Cassiday, T. Koh, C. Gerveshi, G. Wilson, J. Kumar","doi":"10.1109/ISSCC.1987.1157098","DOIUrl":null,"url":null,"abstract":"This report will describe a programmable signal processor with a pipelined arithemetic unit capable of 40 MIPs operation in graph search kernel operations. Thus a fivefold improvement in speech and image processing algorithms can be obtained over conventional architectures The chip was fabricated in a 1.5μm CMOS technology, occupies 43.4mm2and operates at 20MHz.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"166 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A processor for graph search algorithms\",\"authors\":\"S. Glinski, T. M. Lalumia, D. Cassiday, T. Koh, C. Gerveshi, G. Wilson, J. Kumar\",\"doi\":\"10.1109/ISSCC.1987.1157098\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This report will describe a programmable signal processor with a pipelined arithemetic unit capable of 40 MIPs operation in graph search kernel operations. Thus a fivefold improvement in speech and image processing algorithms can be obtained over conventional architectures The chip was fabricated in a 1.5μm CMOS technology, occupies 43.4mm2and operates at 20MHz.\",\"PeriodicalId\":102932,\"journal\":{\"name\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"166 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1987.1157098\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157098","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This report will describe a programmable signal processor with a pipelined arithemetic unit capable of 40 MIPs operation in graph search kernel operations. Thus a fivefold improvement in speech and image processing algorithms can be obtained over conventional architectures The chip was fabricated in a 1.5μm CMOS technology, occupies 43.4mm2and operates at 20MHz.
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