采用布局方法减少CMOS卡开故障，提高可测试性

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157176

S. Koeppe

引用次数: 2

摘要

将分析CMOS布局规则，该规则可将卡开故障减少30%至40%，并使剩余的卡开测试模式可检测到。禁区罚球率低于20%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Layout methods to reduce CMOS stuck-open faults and enhance testability

CMOS layout rules that reduce the stuck-open faults by 30 to 40% and render the remaining detectagle with usual stuck-at test patterns, will be analyzed. The area penalty is less than 20%.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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