发布求助
文献互助 智能选刊 最新文献

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

筛选
英文 中文
A CMOS-CCD signal processor for skew compensation 一种用于倾斜补偿的CMOS-CCD信号处理器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157116
H. Miura, I. Masuda, M. Sato
{"title":"A CMOS-CCD signal processor for skew compensation","authors":"H. Miura, I. Masuda, M. Sato","doi":"10.1109/ISSCC.1987.1157116","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157116","url":null,"abstract":"This paper will cover a CMOS-CCD signal processor with 100mW power consumption for skew compensation in video recorders. Device has three CCD registers merged into one common output circuit, a timing generator, clock drivers, sample and hold and skew detector.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126817178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Future trends in nonvolatile memories 非易失性存储器的未来趋势
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157075
P. Suciu
{"title":"Future trends in nonvolatile memories","authors":"P. Suciu","doi":"10.1109/ISSCC.1987.1157075","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157075","url":null,"abstract":"Key areas to be assessed by the panelists are the merits of non-volatile memory techniques, tradeoffs between them and forecasts of trends in the next decade. Additionally, user and manufacturer panelists will probe the future of EPROMs, flash E2PROMs and E2PROMs.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133649354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital ICs with embedded memory 带有嵌入式存储器的数字集成电路
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157165
J. Barnes
{"title":"Digital ICs with embedded memory","authors":"J. Barnes","doi":"10.1109/ISSCC.1987.1157165","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157165","url":null,"abstract":"The design and testing of logic circuits with large amounts of embedded memory will be discussed. Since the design must encompass both logic and memory portions, problems such as compatible design rules technologies and design tools uniquely exist in this type of chip design. The use of scan paths to test the memory portion of the chip, built-in self-test features, test vector generation and interactions of logic/memory test vector will be described . . . Key areas to be addressed are the amount of modularity and flexibility in the memory core, and the performance advantages expected from embedding.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132378931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A sub-micron CMOS echo canceller using a DSP cell 使用DSP单元的亚微米CMOS回声消除器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157089
H. Takahashi, S. Fujii, K. Kawauchi, T. Inaba, H. Gambe
{"title":"A sub-micron CMOS echo canceller using a DSP cell","authors":"H. Takahashi, S. Fujii, K. Kawauchi, T. Inaba, H. Gambe","doi":"10.1109/ISSCC.1987.1157089","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157089","url":null,"abstract":"This report will cover a 45K gate chip designed using a silicon compiler. A 11.5×11.8mm die contains a DSP that was available as a pre-designed cell.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128119621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VHF-UHF GaAs monolithic front end VHF-UHF GaAs 单片式前端
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157175
P. Dautriche, V. Pauker, A. Collet, C. Villalon
{"title":"VHF-UHF GaAs monolithic front end","authors":"P. Dautriche, V. Pauker, A. Collet, C. Villalon","doi":"10.1109/ISSCC.1987.1157175","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157175","url":null,"abstract":"A pair of GaAs ICs which form a complete front end for a VHF-UHF receiver will be described. The chip set includes an AGC amplifier, two mixers, a VCO, a divide-by-two, a pair of amplifiers and an active combiner. Image rejection is 40dB at 800MHz. Total chip area is 2.15mm2.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134094536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 5ns access time 64Kb ECL RAM 一个5ns访问时间64Kb ECL RAM
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157113
T. Awaya, K. Toyoda, O. Nomura, Y. Nakaya, K. Tanaka, H. Sugawara
{"title":"A 5ns access time 64Kb ECL RAM","authors":"T. Awaya, K. Toyoda, O. Nomura, Y. Nakaya, K. Tanaka, H. Sugawara","doi":"10.1109/ISSCC.1987.1157113","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157113","url":null,"abstract":"An 8K×8 bipolar ECL RAM with segmented bit lines and Darlington drive circuits will be described. RAM uses the sharing signal line technique. Wafer process yield is obtained by use of a memory cell with deep P-well base diffusion and two row redundancy.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"58 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113962332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A four quadrant MOS analog multiplier 四象限MOS模拟倍增器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157181
J. Pena-Finol, J. Connelly
{"title":"A four quadrant MOS analog multiplier","authors":"J. Pena-Finol, J. Connelly","doi":"10.1109/ISSCC.1987.1157181","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157181","url":null,"abstract":"An MOS analog multiplier based on the square law algebraic identity will be covered. The multiplier achieves a nonlinearity of 9.44%, a bandwidth of 5MHz, dynamic range of 87dB and total harmonic distortion of 0.59%. The chip was fabricated with a 5μm P-well CMOS process. Size is 500mil2and total power consumption is 10mW.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"66 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114060568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 4Gb/s limiting amplifier for optical-fiber receivers 一种用于光纤接收器的4Gb/s限制放大器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157093
R. Reimann, H. Rein
{"title":"A 4Gb/s limiting amplifier for optical-fiber receivers","authors":"R. Reimann, H. Rein","doi":"10.1109/ISSCC.1987.1157093","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157093","url":null,"abstract":"This paper will cover a limiting amplifier with 54dB gain obtained by using a cascase of 3 differential gain stages. A 400mV output with low jitter at 4GHz has resulted for inputs ranging from 2.5mV-400mV. The amplifier was fabricated in a 2μm bipolar process and dissipates 350mW.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129077175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A matched impedance NMOS amplifier 匹配阻抗NMOS放大器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157122
K.-y. Toh, R. Meyer, D. Soo, G. Chin, A. Voshchenkov
{"title":"A matched impedance NMOS amplifier","authors":"K.-y. Toh, R. Meyer, D. Soo, G. Chin, A. Voshchenkov","doi":"10.1109/ISSCC.1987.1157122","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157122","url":null,"abstract":"Active shunt feedback and matched amplifiers yielding a 16.35dB gain block with input VSWR less than 2.5, and a 6.7dB noise figure will be discussed. A bandwidth of 758MHz has been achieved in a 1μm NMOS process.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117057704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A video signal processing 20ns 2K × 8 multi-functional memory 视频信号处理20ns 2K × 8多功能存储器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157170
S. Matsumoto, I. Nakagawa, K. Kondo, N. Kojima, N. Tanimura, S. Ishikawa
{"title":"A video signal processing 20ns 2K × 8 multi-functional memory","authors":"S. Matsumoto, I. Nakagawa, K. Kondo, N. Kojima, N. Tanimura, S. Ishikawa","doi":"10.1109/ISSCC.1987.1157170","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157170","url":null,"abstract":"A 20ns serial access static memory with separated asynchronous I/O points Will be described. It has several functional modes, is fabricated in a 1.3μm CMOS process and occupies a chip area of 16.77mm2.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116673362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信