Digital ICs with embedded memory

Abstract

The design and testing of logic circuits with large amounts of embedded memory will be discussed. Since the design must encompass both logic and memory portions, problems such as compatible design rules technologies and design tools uniquely exist in this type of chip design. The use of scan paths to test the memory portion of the chip, built-in self-test features, test vector generation and interactions of logic/memory test vector will be described . . . Key areas to be addressed are the amount of modularity and flexibility in the memory core, and the performance advantages expected from embedding.