1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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A 60ns 4Mb CMOS DRAM with built-in self-test 内置自检的60ns 4Mb CMOS DRAM
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157105
T. Ohsawa, T. Furuyama, Y. Watanabe, H. Tanaka, N. Kushiyama, K. Tsuchida, Y. Nagahama, S. Yamano, T. Tanaka, S. Shinozaki, K. Natori
{"title":"A 60ns 4Mb CMOS DRAM with built-in self-test","authors":"T. Ohsawa, T. Furuyama, Y. Watanabe, H. Tanaka, N. Kushiyama, K. Tsuchida, Y. Nagahama, S. Yamano, T. Tanaka, S. Shinozaki, K. Natori","doi":"10.1109/ISSCC.1987.1157105","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157105","url":null,"abstract":"data transfer time from sense amplifiers to data out buffer. As shown in Figure 1: the RAM has been implemented with eight DQ line pairs for each 512K cell array, leading eight data bits to eight DQ buffers. This configuration reduces the DQ line capacitance, especially junction capacitance of the drain area of DQ gate transistors, because the number of DQ gates connected to one DQ line is inversely proportional to the number of DQ lines. Thus a high speed DQ line sensing can be realized. According to a circuit simulation, the design afforded a saving of 8ns, when compared with an earlier experimental 4Mb DR.4M’. The development is also compatible with the multi-bit parallel test mode. Since two 512K cell arrays are operating in each active cycle, 16b parallel testing can be implemented. The multi-bit parallel test mode, which was first implemented in lMb DRAMs”~ helps to reduce RAM test time. However, a memory unit in a system, such as a main memory of a large computer system, still consumes a very long test time. A self-test function reduces this test time and simplifies test procedure. Figure 2 shows the block diagram of this concept. This function allows all of the chips on a memory board to be tested simultaneously as well as automatically. In the self-test operation, once the DRAM entersinto the mode by the CAS before RAS signal sequence with WE low a e e specified address combination, only the m b e f o r e RAS signal is needed io test the whole 441 memory cells, as shown in Figure 3. A column address counter, connected subsequent to the row address counter for the conventional refresh operation, counts addresses for scanning the whole 4M cells in row fast scan manner. The R.411 also has a test pattern generator and a data comparator. In the first 256K cycles, a checkerboard pattern is written into the 4M cells in the 16b parallel mode. In the next 256K cycles, 16b per cycle are read out and compared For achieving a fast access time, it is important to reduce the","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115718446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 30ns-32b programmable arithmetic operator 30ns-32b可编程算术运算符
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157232
G. Boudon, P. Mollier, J. Nuez, F. Wallart
{"title":"A 30ns-32b programmable arithmetic operator","authors":"G. Boudon, P. Mollier, J. Nuez, F. Wallart","doi":"10.1109/ISSCC.1987.1157232","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157232","url":null,"abstract":"This paper will cover a programmable arithmetic operator implemented in a 6.9×7.1mm gate array chip containing 6000 logic ceils, dissipating less than 1W. The measured gate array is 200ps in a 0.5μm CMOS technology.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"125 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124267243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 32b LISP processor 32b LISP处理器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157173
K. Watanabe, A. Ishikawa, Y. Yamada, Y. Hibino
{"title":"A 32b LISP processor","authors":"K. Watanabe, A. Ishikawa, Y. Yamada, Y. Hibino","doi":"10.1109/ISSCC.1987.1157173","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157173","url":null,"abstract":"A 80K transistor chip, implemented in 2μm CMOS, with a die size of 15×15mm, will be disclosed. A LISP computer assembled with this circuit operates 3X faster than comparable machines.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122781864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A pipelined 5MHz 9b ADC 一个流水线5MHz 9b ADC
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157169
S. Lewis, P. Gray
{"title":"A pipelined 5MHz 9b ADC","authors":"S. Lewis, P. Gray","doi":"10.1109/ISSCC.1987.1157169","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157169","url":null,"abstract":"This paper will report on a 5Msamples/s 9b analog to digital converter in a 3μm CMOS process, which requires 3500 square mils, consumes 18mW, has an Input capacitance of 3pF and uses a fully differential architecture. Digital error correction makes the converter insensitive to comparator offset errors.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 31","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131501311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 1ns Josephson 16b ALU A 1ns约瑟夫逊16b ALU
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157153
S. Kotani, N. Fujimaki, T. Imamura, S. Hasuo
{"title":"A 1ns Josephson 16b ALU","authors":"S. Kotani, N. Fujimaki, T. Imamura, S. Hasuo","doi":"10.1109/ISSCC.1987.1157153","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157153","url":null,"abstract":"A Josephson ALU consisting of 900 variable threshold logic gates will be disclosed. The critical path delay which measures 1.05ns has been obtained at a power consumption of 7 5mW. The average gate delay on the 1.5×8.8mm ALU is estimated to be 11.5ps.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115022005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 30-MFLOPS CMOS single precision floating point multiply/accumulate chip 一个30 mflops的CMOS单精度浮点乘法/累加芯片
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157192
D. Staver, Chung-Yih Ho, K. Molnar, R. Baertsch
{"title":"A 30-MFLOPS CMOS single precision floating point multiply/accumulate chip","authors":"D. Staver, Chung-Yih Ho, K. Molnar, R. Baertsch","doi":"10.1109/ISSCC.1987.1157192","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157192","url":null,"abstract":"A 32b floating point IC, implemented in a 1.2μm CMOS technology, will be described. A pipeline rate of 15MHz has been obtained at a 30MHz clock rate. The 56K transistor chip measures 7.2×8mm.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130346217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 384Kb/s ISDN burst transceiver 一个384Kb/s的ISDN突发收发器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157077
G. Smolka, G. Weinberger, L. Rademacher, G. Geiger
{"title":"A 384Kb/s ISDN burst transceiver","authors":"G. Smolka, G. Weinberger, L. Rademacher, G. Geiger","doi":"10.1109/ISSCC.1987.1157077","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157077","url":null,"abstract":"A 2μm CMOS time-division multiplexed transceiver will be discussed An automatic line equalizer handles cables with up to 32dB insertion loss. The 29mm2chip dissipates 60mW at 5V.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132349718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 7.4ns CMOS 16 × 16 multiplier 7.4ns CMOS 16 × 16倍频器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157168
Y. Oowaki, K. Numata, K. Tsuchiya, K. Tsuda, A. Nitayama, S. Watanbe
{"title":"A 7.4ns CMOS 16 × 16 multiplier","authors":"Y. Oowaki, K. Numata, K. Tsuchiya, K. Tsuda, A. Nitayama, S. Watanbe","doi":"10.1109/ISSCC.1987.1157168","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157168","url":null,"abstract":"A CMOS 16×16b multiplier with submicrometer gatelength, incorporating a modified array implementing Booth's algorithm will be discussed. The multiplication time is 7.4ns for 3V operation, with 400mW dissipation at a 10MHz clock rate.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116394277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A VLSI chip set for a massively parallel architecture 用于大规模并行架构的VLSI芯片组
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157087
R. Grondalski
{"title":"A VLSI chip set for a massively parallel architecture","authors":"R. Grondalski","doi":"10.1109/ISSCC.1987.1157087","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157087","url":null,"abstract":"This paper will described two chips fabricated in 2μms CMOS. One chip contains 32 processors, and performs 320 million 4bit operations/s. The other chip a communications router, is capable of a throughput of 160Mbytes/s.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116440542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A trimmable P-channel JFET quad opamp 一种可调谐p沟道JFET四极运放
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157094
R. Vyne, W. Davis, D. Susak
{"title":"A trimmable P-channel JFET quad opamp","authors":"R. Vyne, W. Davis, D. Susak","doi":"10.1109/ISSCC.1987.1157094","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157094","url":null,"abstract":"A 10μV offset opamp obtained by analog trimming will be reported. The circuit has a 100MHz gain-bandwidth product and a 25V/μs slew rate, using feedforward and local positive feedback. Die size is 80×120mils, and input offset current is 6pA.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134639846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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