A 1ns Josephson 16b ALU

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157153

S. Kotani, N. Fujimaki, T. Imamura, S. Hasuo

引用次数: 7

Abstract

A Josephson ALU consisting of 900 variable threshold logic gates will be disclosed. The critical path delay which measures 1.05ns has been obtained at a power consumption of 7 5mW. The average gate delay on the 1.5×8.8mm ALU is estimated to be 11.5ps.

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A 1ns约瑟夫逊16b ALU

公开了一种由900个可变阈值逻辑门组成的约瑟夫森ALU。在功耗为75mw的情况下，获得了1.05ns的关键路径延迟。1.5×8.8mm ALU上的平均门延迟估计为11.5ps。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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