{"title":"An 8Kbyte intelligent cache memory","authors":"T. Watanabe","doi":"10.1109/ISSCC.1987.1157109","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157109","url":null,"abstract":"WITH THE ADVENT OF FIKE-LINE fabrication technology and incorporation of pipelining architecture, recent single-chip microprocessors have maximum speed as high as several MIPS. On the other hand, the speed of the system bus is relatively low because of slower main memories. To fill this speed gap, the use of cache memories in a microprocessor system has become commonplace. Some modern microprocessors have on-chip memories, and one related paper’ introduced a dedicated chip for the cache memory and memory management unit. A general-purpose intelligent cache memory with 8Kbyte data memories and support functions, will be reported. Four design goals were: compatibility with most high-performance 16b and 32b microprocessor^^'^'^, no-wait cycles at MPU clock rates of 16MHz or higher, cache-miss ratio of less than 57’0, and expandability to a multi-processor system. The first two requirements require the cache memory to operate at an access time of less than 70ns from address strobe signal to ready signal, and at an access time of less than 85ns from address strobe signal to data valid. Tradeoffs between including a larger data memory and integrating more control functions in the cache chip were examined by computer simulation to obtain a solution to the cache-miss ratio. Simulation showed that a data memory of more than 8Kbytes should be introduced on one chip, even if sophisticated housekeeping techniques could be adopted. The best approach was revealed to be the combination of a 4-way set associative placement algorithm, 16bytes block size, L R U replacement algorithm, and use of pre-fetch.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116159256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Hinata, A. Ohtsuka, K. Kaneko, J. Korematsu, K. Nishida, H. Shimoyama, O. Tomisawa, Y. Nishiwaki, H. Kimura
{"title":"A 32b full custom CPU","authors":"J. Hinata, A. Ohtsuka, K. Kaneko, J. Korematsu, K. Nishida, H. Shimoyama, O. Tomisawa, Y. Nishiwaki, H. Kimura","doi":"10.1109/ISSCC.1987.1157129","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157129","url":null,"abstract":"A two-chip 32b VLSI CPU chip set with a cycle time of less than 200ns, using a 1.3μm double-level metal process will be reported. Chip contains 242K transistors sized at 8.75×11.26mm for an average density of 0.65 square mils per transistor.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116393828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modular embedded cache memories for a 32b pipelined RISC microprocessor","authors":"K. O'Connor","doi":"10.1109/ISSCC.1987.1157111","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157111","url":null,"abstract":"Seven CMOS cache SRAM units with 13K of storage and 100K transistors in a 6-stage pipeline, will be reported. Three major sections implement instruction prefetching in two modules of 616bytes, decoded instruction storage in a 32-entry by a 192b assembly and stack references in a dual-ported 32 entry by 64b module. Access time of below 25ns and effective peak data rates in excess of 900Mbytes/s have been achieved.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Yamashina, T. Enomoto, T. Kunio, I. Tamitani, H. Harasaki, T. Nishitani, M. Sato, K. Kikuchi
{"title":"A realtime microprogrammable video signal LSI","authors":"M. Yamashina, T. Enomoto, T. Kunio, I. Tamitani, H. Harasaki, T. Nishitani, M. Sato, K. Kikuchi","doi":"10.1109/ISSCC.1987.1157138","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157138","url":null,"abstract":"A signal processor employing a 3-stage pipelined architecture for efficient realtime video operations, such as edge filtering, motion picture coding and motion compensation, will be reported. Chip incorporates a peak value detector allowing high-speed vector quantization and pattern matching operation. The chip (94.5mm2) uses a 2.5μ CMOS double layer metal process and operates at 14.3MHz.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124161702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A programmable signal processor for array applications","authors":"F. Schlereth, J. Irwin, N. Wild, M. French","doi":"10.1109/ISSCC.1987.1157133","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157133","url":null,"abstract":"A general purpose DSP circuit performing pre-programmed functions such as a 256 point FFT in 500μs in under 400μs will be described. Systolic arrays of the device can perform a 1024-point FFT in 500μs. A 155K transistor chip has been fabricated in 1.25μm CMOS on a die area of 66.9mm2, and operates at 12MHz.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129064136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Program committee 87 ISSCC","authors":"","doi":"10.1109/ISSCC.1987.1157198","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157198","url":null,"abstract":"Provides a listing of current committee members.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117048184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Roberts, J. Dreibelbis, G. Braceras, J. Gabric, L. Gilbert, R. Goodwin, E. Hedberg, T. Maffitt, L. Meuniar, D. Moran, P. Nguyen, D. Reed, D. Reismiller, R. Sasaki
{"title":"A 256K SRAM with on-chip power supply conversion","authors":"A. Roberts, J. Dreibelbis, G. Braceras, J. Gabric, L. Gilbert, R. Goodwin, E. Hedberg, T. Maffitt, L. Meuniar, D. Moran, P. Nguyen, D. Reed, D. Reismiller, R. Sasaki","doi":"10.1109/ISSCC.1987.1157185","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157185","url":null,"abstract":"A 47.2mm2SRAM utilizing an on-chip power supply conversion and allowing full synchronous operation at either 5.0V or 3.3V pin voltage without performance penalty will be discussed. The chip with a six-device cell size of 109μm2has been built in a 0.7μm CMOS DRAM technology with silicides and double level metal. Access times is 30ns, with less than 100mA active current consumption.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"63 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124355744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Marston, G. Burroughs, K. Chen, A. Desroches, G. Emerson, J. Hsu, R. Lee, F. Najami, A. Peebles, K. Peterson, B. Saperstein, J. Wangunhardjo, A. Wiemann, R. Wu
{"title":"A 32b CMOS single-chip RISC type processor","authors":"A. Marston, G. Burroughs, K. Chen, A. Desroches, G. Emerson, J. Hsu, R. Lee, F. Najami, A. Peebles, K. Peterson, B. Saperstein, J. Wangunhardjo, A. Wiemann, R. Wu","doi":"10.1109/ISSCC.1987.1157145","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157145","url":null,"abstract":"A fully custom 164K Transistor Reduced Instruction Set Computer will be discussed. Peak performance is 8MIPS at a frequency of 8MHz. A 1.6μm CMOS technology provides a 8.46mm×8.62mm chip that dissipates 1W.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124446237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A technology commentary - The 30th anniversary of the digest","authors":"R. Swartz","doi":"10.1109/ISSCC.1987.1157137","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157137","url":null,"abstract":"The yearv1987, marks the 40th year of the transistor and the 30th year that the ISSCC Digest of Technical Papers has celebrated the application of semiconductor science. This paper attempts to give perspective to the field, moving backward in time to the first decade of the ISSCC DIGEST, that period extending from 1958 to 1967. The DIGEST will be our lamp, illuminating that vital second decade following the invention of the transistor. It was one of the seminal importance as transistor technology progressed from discrete devices to Large Scale Integration.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"799 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131600360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Masuda, S. Koazechi, T. Mizuta, K. Kimura, K. Matsumoto, Y. Kitamura
{"title":"A CMOS analog and digital master slice LSI","authors":"S. Masuda, S. Koazechi, T. Mizuta, K. Kimura, K. Matsumoto, Y. Kitamura","doi":"10.1109/ISSCC.1987.1157088","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157088","url":null,"abstract":"A 1.6μm CMOS array with programmable aspect-ratio transistors and double-poly capacitors will be described. Using a 7.1×7.5mm array, a modem for mobile telephones has been realized with 17K transistors and 7300 passive elements.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121639664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}