An 8Kbyte intelligent cache memory

Abstract

WITH THE ADVENT OF FIKE-LINE fabrication technology and incorporation of pipelining architecture, recent single-chip microprocessors have maximum speed as high as several MIPS. On the other hand, the speed of the system bus is relatively low because of slower main memories. To fill this speed gap, the use of cache memories in a microprocessor system has become commonplace. Some modern microprocessors have on-chip memories, and one related paper’ introduced a dedicated chip for the cache memory and memory management unit. A general-purpose intelligent cache memory with 8Kbyte data memories and support functions, will be reported. Four design goals were: compatibility with most high-performance 16b and 32b microprocessor^^'^'^, no-wait cycles at MPU clock rates of 16MHz or higher, cache-miss ratio of less than 57’0, and expandability to a multi-processor system. The first two requirements require the cache memory to operate at an access time of less than 70ns from address strobe signal to ready signal, and at an access time of less than 85ns from address strobe signal to data valid. Tradeoffs between including a larger data memory and integrating more control functions in the cache chip were examined by computer simulation to obtain a solution to the cache-miss ratio. Simulation showed that a data memory of more than 8Kbytes should be introduced on one chip, even if sophisticated housekeeping techniques could be adopted. The best approach was revealed to be the combination of a 4-way set associative placement algorithm, 16bytes block size, L R U replacement algorithm, and use of pre-fetch.