用于32b流水线RISC微处理器的模块化嵌入式缓存存储器

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157111

K. O'Connor

{"title":"用于32b流水线RISC微处理器的模块化嵌入式缓存存储器","authors":"K. O'Connor","doi":"10.1109/ISSCC.1987.1157111","DOIUrl":null,"url":null,"abstract":"Seven CMOS cache SRAM units with 13K of storage and 100K transistors in a 6-stage pipeline, will be reported. Three major sections implement instruction prefetching in two modules of 616bytes, decoded instruction storage in a 32-entry by a 192b assembly and stack references in a dual-ported 32 entry by 64b module. Access time of below 25ns and effective peak data rates in excess of 900Mbytes/s have been achieved.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Modular embedded cache memories for a 32b pipelined RISC microprocessor\",\"authors\":\"K. O'Connor\",\"doi\":\"10.1109/ISSCC.1987.1157111\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Seven CMOS cache SRAM units with 13K of storage and 100K transistors in a 6-stage pipeline, will be reported. Three major sections implement instruction prefetching in two modules of 616bytes, decoded instruction storage in a 32-entry by a 192b assembly and stack references in a dual-ported 32 entry by 64b module. Access time of below 25ns and effective peak data rates in excess of 900Mbytes/s have been achieved.\",\"PeriodicalId\":102932,\"journal\":{\"name\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1987.1157111\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157111","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

将报道7个CMOS缓存SRAM单元，具有13K存储空间和6级流水线中的100K晶体管。三个主要部分在两个616字节的模块中实现指令预取，在一个192b汇编中以32项的方式解码指令存储，以及在一个双端口32项的64b模块中实现堆栈引用。访问时间低于25ns，有效峰值数据速率超过900mb /s。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Modular embedded cache memories for a 32b pipelined RISC microprocessor

Seven CMOS cache SRAM units with 13K of storage and 100K transistors in a 6-stage pipeline, will be reported. Three major sections implement instruction prefetching in two modules of 616bytes, decoded instruction storage in a 32-entry by a 192b assembly and stack references in a dual-ported 32 entry by 64b module. Access time of below 25ns and effective peak data rates in excess of 900Mbytes/s have been achieved.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

自引率

0.00%

发文量