Modular embedded cache memories for a 32b pipelined RISC microprocessor

Abstract

Seven CMOS cache SRAM units with 13K of storage and 100K transistors in a 6-stage pipeline, will be reported. Three major sections implement instruction prefetching in two modules of 616bytes, decoded instruction storage in a 32-entry by a 192b assembly and stack references in a dual-ported 32 entry by 64b module. Access time of below 25ns and effective peak data rates in excess of 900Mbytes/s have been achieved.