J. Hinata, A. Ohtsuka, K. Kaneko, J. Korematsu, K. Nishida, H. Shimoyama, O. Tomisawa, Y. Nishiwaki, H. Kimura
{"title":"一个32b全自定义CPU","authors":"J. Hinata, A. Ohtsuka, K. Kaneko, J. Korematsu, K. Nishida, H. Shimoyama, O. Tomisawa, Y. Nishiwaki, H. Kimura","doi":"10.1109/ISSCC.1987.1157129","DOIUrl":null,"url":null,"abstract":"A two-chip 32b VLSI CPU chip set with a cycle time of less than 200ns, using a 1.3μm double-level metal process will be reported. Chip contains 242K transistors sized at 8.75×11.26mm for an average density of 0.65 square mils per transistor.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 32b full custom CPU\",\"authors\":\"J. Hinata, A. Ohtsuka, K. Kaneko, J. Korematsu, K. Nishida, H. Shimoyama, O. Tomisawa, Y. Nishiwaki, H. Kimura\",\"doi\":\"10.1109/ISSCC.1987.1157129\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A two-chip 32b VLSI CPU chip set with a cycle time of less than 200ns, using a 1.3μm double-level metal process will be reported. Chip contains 242K transistors sized at 8.75×11.26mm for an average density of 0.65 square mils per transistor.\",\"PeriodicalId\":102932,\"journal\":{\"name\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1987.1157129\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157129","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A two-chip 32b VLSI CPU chip set with a cycle time of less than 200ns, using a 1.3μm double-level metal process will be reported. Chip contains 242K transistors sized at 8.75×11.26mm for an average density of 0.65 square mils per transistor.