M. Yamashina, T. Enomoto, T. Kunio, I. Tamitani, H. Harasaki, T. Nishitani, M. Sato, K. Kikuchi
{"title":"一种实时微可编程视频信号LSI","authors":"M. Yamashina, T. Enomoto, T. Kunio, I. Tamitani, H. Harasaki, T. Nishitani, M. Sato, K. Kikuchi","doi":"10.1109/ISSCC.1987.1157138","DOIUrl":null,"url":null,"abstract":"A signal processor employing a 3-stage pipelined architecture for efficient realtime video operations, such as edge filtering, motion picture coding and motion compensation, will be reported. Chip incorporates a peak value detector allowing high-speed vector quantization and pattern matching operation. The chip (94.5mm2) uses a 2.5μ CMOS double layer metal process and operates at 14.3MHz.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A realtime microprogrammable video signal LSI\",\"authors\":\"M. Yamashina, T. Enomoto, T. Kunio, I. Tamitani, H. Harasaki, T. Nishitani, M. Sato, K. Kikuchi\",\"doi\":\"10.1109/ISSCC.1987.1157138\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A signal processor employing a 3-stage pipelined architecture for efficient realtime video operations, such as edge filtering, motion picture coding and motion compensation, will be reported. Chip incorporates a peak value detector allowing high-speed vector quantization and pattern matching operation. The chip (94.5mm2) uses a 2.5μ CMOS double layer metal process and operates at 14.3MHz.\",\"PeriodicalId\":102932,\"journal\":{\"name\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1987.1157138\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157138","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A signal processor employing a 3-stage pipelined architecture for efficient realtime video operations, such as edge filtering, motion picture coding and motion compensation, will be reported. Chip incorporates a peak value detector allowing high-speed vector quantization and pattern matching operation. The chip (94.5mm2) uses a 2.5μ CMOS double layer metal process and operates at 14.3MHz.