A. Marston, G. Burroughs, K. Chen, A. Desroches, G. Emerson, J. Hsu, R. Lee, F. Najami, A. Peebles, K. Peterson, B. Saperstein, J. Wangunhardjo, A. Wiemann, R. Wu
{"title":"32b CMOS单片RISC型处理器","authors":"A. Marston, G. Burroughs, K. Chen, A. Desroches, G. Emerson, J. Hsu, R. Lee, F. Najami, A. Peebles, K. Peterson, B. Saperstein, J. Wangunhardjo, A. Wiemann, R. Wu","doi":"10.1109/ISSCC.1987.1157145","DOIUrl":null,"url":null,"abstract":"A fully custom 164K Transistor Reduced Instruction Set Computer will be discussed. Peak performance is 8MIPS at a frequency of 8MHz. A 1.6μm CMOS technology provides a 8.46mm×8.62mm chip that dissipates 1W.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 32b CMOS single-chip RISC type processor\",\"authors\":\"A. Marston, G. Burroughs, K. Chen, A. Desroches, G. Emerson, J. Hsu, R. Lee, F. Najami, A. Peebles, K. Peterson, B. Saperstein, J. Wangunhardjo, A. Wiemann, R. Wu\",\"doi\":\"10.1109/ISSCC.1987.1157145\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully custom 164K Transistor Reduced Instruction Set Computer will be discussed. Peak performance is 8MIPS at a frequency of 8MHz. A 1.6μm CMOS technology provides a 8.46mm×8.62mm chip that dissipates 1W.\",\"PeriodicalId\":102932,\"journal\":{\"name\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1987.1157145\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157145","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fully custom 164K Transistor Reduced Instruction Set Computer will be discussed. Peak performance is 8MIPS at a frequency of 8MHz. A 1.6μm CMOS technology provides a 8.46mm×8.62mm chip that dissipates 1W.