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1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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GaAs switched-capacitor circuits for video signal processing 用于视频信号处理的砷化镓开关电容电路
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157146
L. Larson, K. Martin, G. Temes
{"title":"GaAs switched-capacitor circuits for video signal processing","authors":"L. Larson, K. Martin, G. Temes","doi":"10.1109/ISSCC.1987.1157146","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157146","url":null,"abstract":"This report will cover GaAs circuits for video signal-processing applications at sampling rates from 5-300MHz and signal frequencies from 0-20MHz. Device includes a biquadratic bandpass filter and a 3rd order elliptic ladder low-pass filter which dissipates 300mW and 500mW, respectively.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122056044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A CMOS programmable self-calibrating 13b eight-channel analog interface processor CMOS可编程自校准13b 8通道模拟接口处理器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157148
M. Armstrong, H. Ohara, H. Ngo, C. Rahim, A. Grossman, P. Gray
{"title":"A CMOS programmable self-calibrating 13b eight-channel analog interface processor","authors":"M. Armstrong, H. Ohara, H. Ngo, C. Rahim, A. Grossman, P. Gray","doi":"10.1109/ISSCC.1987.1157148","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157148","url":null,"abstract":"A single-chip programmable analog interface system containing a self-calibrated algorithmic 13b 25μs ADC will be described. The development has an 8-channel multiplexer, programmable instrumentation amplifier, sample and hold, bandgap reference and other interfacing devices.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123082778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An 8ns monolithic GaAs sample and hold amplifier 一个8ns单片砷化镓样品和保持放大器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157149
R. Bayruns, N. Scheinberg, R. Goyal
{"title":"An 8ns monolithic GaAs sample and hold amplifier","authors":"R. Bayruns, N. Scheinberg, R. Goyal","doi":"10.1109/ISSCC.1987.1157149","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157149","url":null,"abstract":"A sample and hold with 8ns acquisition time and 170MHz bandwidth will be described. The device uses ± 5V supplies and dissipates 600mW. The circuit contains a 500MHz operational amplifier, FET switching network and an ECL translator on a 1mm2die.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122841424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 1024-channel multifunction digital switching IC 一种1024通道多功能数字开关集成电路
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157187
K. Ikuzaki, M. Shibukawa, M. Fujita, K. Abe, M. Mizukami, Y. Satoh, K. Asano, E. Amada, S. Yoshida, T. Harkawa
{"title":"A 1024-channel multifunction digital switching IC","authors":"K. Ikuzaki, M. Shibukawa, M. Fujita, K. Abe, M. Mizukami, Y. Satoh, K. Asano, E. Amada, S. Yoshida, T. Harkawa","doi":"10.1109/ISSCC.1987.1157187","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157187","url":null,"abstract":"A 16.3MHz switching IC Implemented in a 1.3μm CMOS technology will be detailed. Functions include bit phase and frame synchronization, 8/16b interface and maintenance tasks. An on-chip 216K RAM with 15ns access time has been implemented. The 8.5mm square chip dissipates 370mW.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122028166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ASIC architectures for the 90s 90年代的ASIC架构
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157164
J. Allen
{"title":"ASIC architectures for the 90s","authors":"J. Allen","doi":"10.1109/ISSCC.1987.1157164","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157164","url":null,"abstract":"Alternatives in Application Specific IC (ASIC), including MOS and bipolar arrays, standard cells, macro-cells, application specific compilers and wafer - scale integration will be compared. Applicable technology, design time, testability, performance, cost and development tools will be discussed from the point of view of the user, the vendor and the CAD tool designer.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127966067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A million-cycle CMOS 256K EEPROM 一个百万周期CMOS 256K EEPROM
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157155
D. Cioaca, Tien Lin, A. Chan, L. Chen, A. Mihnea
{"title":"A million-cycle CMOS 256K EEPROM","authors":"D. Cioaca, Tien Lin, A. Chan, L. Chen, A. Mihnea","doi":"10.1109/ISSCC.1987.1157155","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157155","url":null,"abstract":"This paper will discuss a device with an endurance of 1-million cycles and a read access time of 150ns, fabricated in 1.25μm double poly CMOS. Circuit modes include byte write and page write, with means of endurance selection.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121384817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A piepline sorting chip 流水线分拣芯片
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157107
N. Tsuda, T. Satoh, T. Kawada
{"title":"A piepline sorting chip","authors":"N. Tsuda, T. Satoh, T. Kawada","doi":"10.1109/ISSCC.1987.1157107","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157107","url":null,"abstract":"A 3μm, double metal CMOS pipeline sorter ship that selects 80 16-byte records at a 3Mbytes/s throughput rate will be disclosed. The 37×21mm chip uses hierarchical redundancy and laser repair to increase yield by 10× with an eara of only 1.9×.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122848834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 32b microprocessor with on-chip 2Kbyte instruction cache 带有片上2Kbyte指令缓存的32b微处理器
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157215
M. Horowitz, J. Hennessy, P. Chow, P. Gulak, J. Acken, A. Agarwal, Chorng-Yeung Chu, S. McFarling, S. Przybylski, S. Richardson, A. Salz, R. Simoni, D. Stark, P. Steenkiste, S. Tjiang, M. Wing
{"title":"A 32b microprocessor with on-chip 2Kbyte instruction cache","authors":"M. Horowitz, J. Hennessy, P. Chow, P. Gulak, J. Acken, A. Agarwal, Chorng-Yeung Chu, S. McFarling, S. Przybylski, S. Richardson, A. Salz, R. Simoni, D. Stark, P. Steenkiste, S. Tjiang, M. Wing","doi":"10.1109/ISSCC.1987.1157215","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157215","url":null,"abstract":"A Reduced Instruction Set Computer with a 5-stage pipeline implemented with 150K transistors on an 8mm×8.5mm chip in a 2μm, 2 layer metal CMOS process, will be reported. At operational frequency of 20MHz, a 12MIPS performance has been achieved.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122546349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Educating future chip designers 培养未来的芯片设计师
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157160
M. Horowitz
{"title":"Educating future chip designers","authors":"M. Horowitz","doi":"10.1109/ISSCC.1987.1157160","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157160","url":null,"abstract":"The evolution of analog and digital integrated circuits from small elements to complex systems is clearly documented in the past issues of the DIGEST. Improvements in technology and CAD, raise some vital questions about the areas that future chip designers need to understand and the venue for this training. The answers depend strongly on the techniques and tools available for the chip designer: whether CAD will provide powerful compilers, freeing the designer to focus on system issues, or whether the demands of performance tuning debugging and normal design will force the designer to understand circuits. To discuss these issues, panelists will review opinions on the relative importance of the spectrum from device physics to system architecture.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124670374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A system-level circuit model for multi- and single-chip CPUs 多片和单片cpu的系统级电路模型
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1987.1157231
H. Bakoglu, J. Meindl
{"title":"A system-level circuit model for multi- and single-chip CPUs","authors":"H. Bakoglu, J. Meindl","doi":"10.1109/ISSCC.1987.1157231","DOIUrl":"https://doi.org/10.1109/ISSCC.1987.1157231","url":null,"abstract":"This report will detail a system level circuit model that has been used to predict the performance of microprocessors, gate arrays, and mainframe computers implemented in several IC technologies. Comparisons have been made on the basis of clock frequency, power dissipation and chip/module sizes. Predictions indicate that in ten years a 0.7μm CMOS micro-processor with 6-million transistors will execute 30-60 MIPS.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127153170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
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