带有片上2Kbyte指令缓存的32b微处理器

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157215

M. Horowitz, J. Hennessy, P. Chow, P. Gulak, J. Acken, A. Agarwal, Chorng-Yeung Chu, S. McFarling, S. Przybylski, S. Richardson, A. Salz, R. Simoni, D. Stark, P. Steenkiste, S. Tjiang, M. Wing

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引用次数: 15

摘要

在2μm的2层金属CMOS工艺中，在8mm×8.5mm芯片上使用150K晶体管实现5级流水线的精简指令集计算机。在20MHz的工作频率下，实现了12MIPS的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 32b microprocessor with on-chip 2Kbyte instruction cache

A Reduced Instruction Set Computer with a 5-stage pipeline implemented with 150K transistors on an 8mm×8.5mm chip in a 2μm, 2 layer metal CMOS process, will be reported. At operational frequency of 20MHz, a 12MIPS performance has been achieved.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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