A piepline sorting chip

N. Tsuda, T. Satoh, T. Kawada
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引用次数: 4

Abstract

A 3μm, double metal CMOS pipeline sorter ship that selects 80 16-byte records at a 3Mbytes/s throughput rate will be disclosed. The 37×21mm chip uses hierarchical redundancy and laser repair to increase yield by 10× with an eara of only 1.9×.
流水线分拣芯片
将公开一种3μm的双金属CMOS流水线分拣船,以3mb /s的吞吐量选择80条16字节的记录。37×21mm芯片使用分层冗余和激光修复,以仅1.9倍的损耗将产量提高10倍。
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