7.4ns CMOS 16 × 16倍频器

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157168

Y. Oowaki, K. Numata, K. Tsuchiya, K. Tsuda, A. Nitayama, S. Watanbe

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引用次数: 5

摘要

本文将讨论一种亚微米门长CMOS 16×16b乘法器，该乘法器采用改进的阵列实现Booth算法。在3V工作时，乘法时间为7.4ns，在10MHz时钟速率下损耗为400mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 7.4ns CMOS 16 × 16 multiplier

A CMOS 16×16b multiplier with submicrometer gatelength, incorporating a modified array implementing Booth's algorithm will be discussed. The multiplication time is 7.4ns for 3V operation, with 400mW dissipation at a 10MHz clock rate.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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