A 60ns 4Mb CMOS DRAM with built-in self-test

T. Ohsawa, T. Furuyama, Y. Watanabe, H. Tanaka, N. Kushiyama, K. Tsuchida, Y. Nagahama, S. Yamano, T. Tanaka, S. Shinozaki, K. Natori
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引用次数: 10

Abstract

data transfer time from sense amplifiers to data out buffer. As shown in Figure 1: the RAM has been implemented with eight DQ line pairs for each 512K cell array, leading eight data bits to eight DQ buffers. This configuration reduces the DQ line capacitance, especially junction capacitance of the drain area of DQ gate transistors, because the number of DQ gates connected to one DQ line is inversely proportional to the number of DQ lines. Thus a high speed DQ line sensing can be realized. According to a circuit simulation, the design afforded a saving of 8ns, when compared with an earlier experimental 4Mb DR.4M’. The development is also compatible with the multi-bit parallel test mode. Since two 512K cell arrays are operating in each active cycle, 16b parallel testing can be implemented. The multi-bit parallel test mode, which was first implemented in lMb DRAMs”~ helps to reduce RAM test time. However, a memory unit in a system, such as a main memory of a large computer system, still consumes a very long test time. A self-test function reduces this test time and simplifies test procedure. Figure 2 shows the block diagram of this concept. This function allows all of the chips on a memory board to be tested simultaneously as well as automatically. In the self-test operation, once the DRAM entersinto the mode by the CAS before RAS signal sequence with WE low a e e specified address combination, only the m b e f o r e RAS signal is needed io test the whole 441 memory cells, as shown in Figure 3. A column address counter, connected subsequent to the row address counter for the conventional refresh operation, counts addresses for scanning the whole 4M cells in row fast scan manner. The R.411 also has a test pattern generator and a data comparator. In the first 256K cycles, a checkerboard pattern is written into the 4M cells in the 16b parallel mode. In the next 256K cycles, 16b per cycle are read out and compared For achieving a fast access time, it is important to reduce the
内置自检的60ns 4Mb CMOS DRAM
从感测放大器到数据输出缓冲器的数据传输时间。如图1所示:RAM为每个512K单元阵列实现了8个DQ线对,将8个数据位引导到8个DQ缓冲区。这种配置降低了DQ线电容,特别是DQ栅极晶体管漏极区的结电容,因为连接在一条DQ线上的DQ门的数量与DQ线的数量成反比。从而实现高速DQ线检测。电路仿真表明,与早期实验的4Mb DR.4M相比,该设计可节省8ns。该开发还兼容多比特并行测试模式。由于两个512K单元阵列在每个活动周期中工作,因此可以实现16b并行测试。首先在lMb dram中实现的多比特并行测试模式有助于减少RAM测试时间。然而,系统中的存储单元,例如大型计算机系统的主存储器,仍然需要花费很长的测试时间。自检功能减少了测试时间,简化了测试过程。图2显示了这个概念的框图。此功能允许内存板上的所有芯片同时进行自动测试。在自检操作中,一旦DRAM通过具有WE low和指定地址组合的CAS前RAS信号序列进入模式,则只需要使用RAS信号的m - b - e来测试整个441个存储单元,如图3所示。列地址计数器连接在常规刷新操作的行地址计数器之后,以行快速扫描方式计算扫描整个4M单元的地址。R.411也有一个测试模式生成器和一个数据比较器。在前256K周期中,以16b并行模式将棋盘模式写入4M单元。在接下来的256K周期中,每个周期读取16b并进行比较。为了实现快速的访问时间,重要的是减少
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