T. Ohsawa, T. Furuyama, Y. Watanabe, H. Tanaka, N. Kushiyama, K. Tsuchida, Y. Nagahama, S. Yamano, T. Tanaka, S. Shinozaki, K. Natori
{"title":"A 60ns 4Mb CMOS DRAM with built-in self-test","authors":"T. Ohsawa, T. Furuyama, Y. Watanabe, H. Tanaka, N. Kushiyama, K. Tsuchida, Y. Nagahama, S. Yamano, T. Tanaka, S. Shinozaki, K. Natori","doi":"10.1109/ISSCC.1987.1157105","DOIUrl":null,"url":null,"abstract":"data transfer time from sense amplifiers to data out buffer. As shown in Figure 1: the RAM has been implemented with eight DQ line pairs for each 512K cell array, leading eight data bits to eight DQ buffers. This configuration reduces the DQ line capacitance, especially junction capacitance of the drain area of DQ gate transistors, because the number of DQ gates connected to one DQ line is inversely proportional to the number of DQ lines. Thus a high speed DQ line sensing can be realized. According to a circuit simulation, the design afforded a saving of 8ns, when compared with an earlier experimental 4Mb DR.4M’. The development is also compatible with the multi-bit parallel test mode. Since two 512K cell arrays are operating in each active cycle, 16b parallel testing can be implemented. The multi-bit parallel test mode, which was first implemented in lMb DRAMs”~ helps to reduce RAM test time. However, a memory unit in a system, such as a main memory of a large computer system, still consumes a very long test time. A self-test function reduces this test time and simplifies test procedure. Figure 2 shows the block diagram of this concept. This function allows all of the chips on a memory board to be tested simultaneously as well as automatically. In the self-test operation, once the DRAM entersinto the mode by the CAS before RAS signal sequence with WE low a e e specified address combination, only the m b e f o r e RAS signal is needed io test the whole 441 memory cells, as shown in Figure 3. A column address counter, connected subsequent to the row address counter for the conventional refresh operation, counts addresses for scanning the whole 4M cells in row fast scan manner. The R.411 also has a test pattern generator and a data comparator. In the first 256K cycles, a checkerboard pattern is written into the 4M cells in the 16b parallel mode. In the next 256K cycles, 16b per cycle are read out and compared For achieving a fast access time, it is important to reduce the","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157105","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
data transfer time from sense amplifiers to data out buffer. As shown in Figure 1: the RAM has been implemented with eight DQ line pairs for each 512K cell array, leading eight data bits to eight DQ buffers. This configuration reduces the DQ line capacitance, especially junction capacitance of the drain area of DQ gate transistors, because the number of DQ gates connected to one DQ line is inversely proportional to the number of DQ lines. Thus a high speed DQ line sensing can be realized. According to a circuit simulation, the design afforded a saving of 8ns, when compared with an earlier experimental 4Mb DR.4M’. The development is also compatible with the multi-bit parallel test mode. Since two 512K cell arrays are operating in each active cycle, 16b parallel testing can be implemented. The multi-bit parallel test mode, which was first implemented in lMb DRAMs”~ helps to reduce RAM test time. However, a memory unit in a system, such as a main memory of a large computer system, still consumes a very long test time. A self-test function reduces this test time and simplifies test procedure. Figure 2 shows the block diagram of this concept. This function allows all of the chips on a memory board to be tested simultaneously as well as automatically. In the self-test operation, once the DRAM entersinto the mode by the CAS before RAS signal sequence with WE low a e e specified address combination, only the m b e f o r e RAS signal is needed io test the whole 441 memory cells, as shown in Figure 3. A column address counter, connected subsequent to the row address counter for the conventional refresh operation, counts addresses for scanning the whole 4M cells in row fast scan manner. The R.411 also has a test pattern generator and a data comparator. In the first 256K cycles, a checkerboard pattern is written into the 4M cells in the 16b parallel mode. In the next 256K cycles, 16b per cycle are read out and compared For achieving a fast access time, it is important to reduce the