一个30 mflops的CMOS单精度浮点乘法/累加芯片

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157192

D. Staver, Chung-Yih Ho, K. Molnar, R. Baertsch

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引用次数: 6

摘要

本文将介绍采用1.2μm CMOS技术实现的32b浮点IC。在30MHz的时钟速率下，获得15MHz的流水线速率。56K晶体管芯片的尺寸为7.2×8mm。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 30-MFLOPS CMOS single precision floating point multiply/accumulate chip

A 32b floating point IC, implemented in a 1.2μm CMOS technology, will be described. A pipeline rate of 15MHz has been obtained at a 30MHz clock rate. The 56K transistor chip measures 7.2×8mm.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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